An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.

An integrated circuit packaging is described and includes a plurality of electrical circuits developed using a first patterned conductive layer on a base, wherein the electrical circuit is formed by using a masking material, and a stud conductive layer disposed on at least one side of the first patterned conductive layer developed by a second layer photo-resist material on the masking material, in which the second layer photo-resist material includes a first line layer with a smaller exposed area than the surface of the conductive layer disposed on one side of the first patterned conductive layer and a second line layer with a larger exposed area than the first line layer disposed on the first layer, such that the exposed area forms an “I” shaped connection of the conductive layer and the stud conductive layer.

An integrated circuit packaging is described and includes a plurality of electrical circuits developed using a first patterned conductive layer on a base, wherein the electrical circuit is formed by using a masking material, and a stud conductive layer disposed on at least one side of the first patterned conductive layer developed by a second layer photo-resist material on the masking material, in which the second layer photo-resist material includes a first line layer with a smaller exposed area than the surface of the conductive layer disposed on one side of the first patterned conductive layer and a second line layer with a larger exposed area than the first line layer disposed on the first layer, such that the exposed area forms an “I” shaped connection of the conductive layer and the stud conductive layer.

A semiconductor device includes a first drain region that is made primarily of SiC, a drift layer, a channel region, a first source region, a source electrode that is formed on the first source region, a second drain region that is connected to the first source region, a second source region that is formed separated from the second drain region, a first floating electrode that is connected to the second source region and to the channel region, first gate electrodes, and a second gate electrode that is connected to the first gate electrodes.

A method of processing a workpiece includes: a frame unit preparing step of preparing a frame unit including a tape affixed to an undersurface of the workpiece; a protective film forming step of forming a protective film on a top surface of the workpiece; a cutting step of cutting the workpiece by applying a laser beam; an interval expanding step of widening intervals between chips formed in the cutting step by expanding the tape outward in a radial direction; and an etching step of removing altered regions formed in the respective chips.

A method of processing a workpiece includes: a frame unit preparing step of preparing a frame unit including a tape affixed to an undersurface of the workpiece; a protective film forming step of forming a protective film on a top surface of the workpiece; a cutting step of cutting the workpiece by applying a laser beam; an interval expanding step of widening intervals between chips formed in the cutting step by expanding the tape outward in a radial direction; and an etching step of removing altered regions formed in the respective chips.

A purpose of the invention is to provide a crossbar switch for reducing the layout areas of a crossbar switch and peripheral circuits thereof. A crossbar switch of the invention comprises: a plurality of first wires extending in a first direction; a plurality of second wires extending in a second direction; a plurality of third wires extending in a third direction; a plurality of fourth wires extending in a fourth direction; and a plurality of switch cells connected to the first and second wires. The first wires are skew relative to the second and fourth wires, while the third wires are skew relative to the second and fourth wires. The switch cells are connected to the third and fourth wires, and further, the third wires are also connected to the switch cells connected to the first wires adjacent to the respective first wires; or alternatively, further, the fourth wires are also connected to the switch cells connected to the second wires adjacent to the respective second wires.

Electronic devices are collectively fabricated from a main wafer which includes optical elements and a secondary wafer that are mounted one on top of the other to form a combined wafer. A mounting face of the secondary wafer is mated to a front face of the main wafer in such a manner that recesses within the mounting face of the secondary wafer are aligned over the optical elements. The thickness of the secondary wafer reduced until the recesses are opened to form ring structures with openings at the recesses. The combined wafer is diced to form electronic devices. A base wafer of the main wafer and the secondary wafer are made of a same semiconductor material (for example, silicon).

Electronic devices are collectively fabricated from a main wafer which includes optical elements and a secondary wafer that are mounted one on top of the other to form a combined wafer. A mounting face of the secondary wafer is mated to a front face of the main wafer in such a manner that recesses within the mounting face of the secondary wafer are aligned over the optical elements. The thickness of the secondary wafer reduced until the recesses are opened to form ring structures with openings at the recesses. The combined wafer is diced to form electronic devices. A base wafer of the main wafer and the secondary wafer are made of a same semiconductor material (for example, silicon).

A method of packing a semiconductor device is disclosed. The method includes placing a wafer on a carrier such that a backside of the wafer is facing up and a front side is facing down and non-permanently affixed to the surface of the carrier, performing lithography to mark area to be etched on the backside of the wafer, etching the marked areas from the backside of the wafer thus forming trenches that mark boundaries of individual devices on the wafer, applying a protective coating on the backside of the wafer thus filling the trenches and entire backside of the wafer with a protective compound and cutting the individual devices from the wafer.