In some examples, a device comprises a wafer chuck, a member having a surface facing the wafer chuck, a blade supported by the surface, a first vacuum nozzle extending through the member and having a first vacuum orifice facing a same direction as the surface, and a second vacuum nozzle extending through the member and having a second vacuum orifice facing the same direction as the surface. The first and second vacuum orifices are on opposing sides of the blade.

In some examples, a device comprises a wafer chuck, a member having a surface facing the wafer chuck, a blade supported by the surface, a first vacuum nozzle extending through the member and having a first vacuum orifice facing a same direction as the surface, and a second vacuum nozzle extending through the member and having a second vacuum orifice facing the same direction as the surface. The first and second vacuum orifices are on opposing sides of the blade.

Provided is a semiconductor element capable of inspecting a plurality of wires formed in parallel. A semiconductor element according to an embodiment includes: a first circuit (45B) connected to a first position of each of a plurality of wires of a first wire group (31) including the plurality of wires; a second circuit (45A) connected to a second position corresponding to an end of each of the plurality of wires; and a plurality of connection units (43) that connects a third circuit (14) with each of the plurality of wires, the plurality of connection units (43) being provided on a one-to-one basis to the plurality of wires between the first position and the second position of each of the plurality of wires.

A semiconductor integrated circuit device includes a clock buffer cell that is a standard cell transmitting a clock signal. The clock buffer cell has an input terminal and an output terminal. A first metal interconnect including the output terminal is located in a layer above a second metal interconnect including the input terminal and greater in width than the second metal interconnect.

A quantum dot light-emitting diode substrate having a bonding layer and a method of preparing the same are provided. The quantum dot light-emitting diode substrate including a plurality of sub-pixel light-emitting regions, wherein each of the sub-pixel light-emitting regions includes a light-emitting layer including a bonding layer and a quantum dot bonded to the bonding layer. The quantum dot light-emitting diode substrate can be prepared with high resolution by a convenient process, and is suitable for mass production.

A quantum dot light-emitting diode substrate having a bonding layer and a method of preparing the same are provided. The quantum dot light-emitting diode substrate including a plurality of sub-pixel light-emitting regions, wherein each of the sub-pixel light-emitting regions includes a light-emitting layer including a bonding layer and a quantum dot bonded to the bonding layer. The quantum dot light-emitting diode substrate can be prepared with high resolution by a convenient process, and is suitable for mass production.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.