A resin composition has a high glass transition temperature and is highly adhesive to a member made of metal, ceramics, or the like. The resin composition includes a thermosetting base resin, a thermoplastic resin powder, a curing agent, and an inorganic filler, a cured resin product formed by curing the resin composition, and an electrical member.

A semiconductor device includes a semiconductor module, an insulating resin layer, a frame member, and a heat sink. Insulating resin layer is bonded to semiconductor module and contains a first resin. Frame member is disposed to surround insulating resin layer, and includes a porous material. Heat sink and semiconductor module sandwich insulating resin layer and frame member. Frame member is compressed while being sandwiched between semiconductor module and heat sink. Insulating resin layer is filled in a region surrounded by semiconductor module, heat sink, and frame member. The first resin enters pores of the porous material.

[Problem] To provide a multi-layer sheet for mold underfill encapsulation, which exhibits good infiltrability between electrodes. [Solution] In order to solve the aforementioned problem, the present invention provides a multi-layer sheet for mold underfill encapsulation, which is characterized by having provided as an outermost layer thereof an (A) layer that comprises a resin composition having a local maximum loss tangent (tan δ) value of 3 or more at a measurement temperature of 125° C. for a measurement time of 0-100 seconds.

A semiconductor encapsulation material is used to fabricate a semiconductor device. The semiconductor device includes a semiconductor chip and an encapsulating portion. The encapsulating portion is made of a cured product of the semiconductor encapsulation material. The encapsulating portion encapsulates the semiconductor chip. A stress index (SI), given by the following Formula (1), of the semiconductor encapsulation material is equal to or more than 8500. If a volume of the semiconductor chip is represented by Vc and a total volume of the semiconductor chip and the encapsulating portion is represented by Va, the volume Vc and the total volume Va satisfy the following Formula (2). In Formula (1), E′ (T) represents a storage modulus, CTE (T) represents a coefficient of thermal expansion, and Mold temp. represents a molding temperature.

[00001]$\begin{array}{cc}\mathrm{SI}={\int }_{35°C.}^{\mathrm{Moldtemp}.}\left[E^{\prime }\left(T\right)\times \mathrm{CTE}\left(T\right)\right]\mathrm{dT}& \left(1\right)\\ \frac{\mathrm{Vc}}{\mathrm{Va}}\geqq 0.3.& \left(2\right)\end{array}$

A chip package may include: a first die; at least one second die disposed over the first die; and a lid disposed over lateral portions of the first die and at least partially surrounding the at least one second die, the lid having inclined sidewalls spaced apart from and facing the at least one second die.

Disclosed is a semiconductor device that is configured to contain a sealing layer for sealing a semiconductor element supported on a base, the sealing layer being configured to have a nanocomposite structure that comprises a large number of nanometer-sized (1 μm or smaller) insulating nanoparticles composed of SiO.sub.2, and an amorphous silica matrix that fills up the space around the insulating nanoparticles without voids and gaps.

An epoxy resin composition for encapsulating a semiconductor device and a semiconductor device encapsulated by the epoxy resin composition, the composition including a base resin; a filler; a colorant; and a thermochromic pigment, wherein a color of the thermochromic pigment is irreversibly changed when a temperature thereof exceeds a predetermined temperature.

Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.

An electronic component has an organic member between two transparent substrates, in which outer peripheral portions of the two transparent substrates are bonded by a sealing material containing to melting glass. The low melting glass contains vanadium oxide, tellurium oxide, iron oxide and phosphoric acid, and satisfies the following relations (1) and (2) in terms of oxides. The sealing material is formed of a sealing material paste which contains the low melting glass, a resin binder and a solvent, the low melting glass containing vanadium oxide, tellurium oxide, iron oxide and phosphoric acid, and satisfies the following relations (1) and (2) in terms of the oxides. Thereby, thermal damages to an organic element or an organic material contained in the electronic component can be reduced and an electronic component having a glass bonding layer of high reliability can be produced efficiently.
V.sub.2O.sub.5+TeO.sub.2+Fe.sub.2O+P.sub.2O.sub.5≧90(mass %)  (1)
V.sub.2O.sub.5>TeO.sub.2>Fe.sub.2O.sub.3>P.sub.2O.sub.5 (mass %)  (2)

A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.