A semiconductor module includes a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a reinforcing structure contained within the interior volume and including a textured surface that is accessible by fluid, a volume of curable encapsulant disposed within the interior volume and encapsulating the power semiconductor die, wherein the reinforcing structure is embedded within the volume of curable encapsulant such that the textured surface adheres to the encapsulant, and wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant.

A semiconductor module includes a mounting substrate, a transistor mounted on the mounting substrate, a housing configured to house a semiconductor element, a first sealing layer filled in a space inside the housing to seal the transistor, a second sealing layer of a resin material softer than the first sealing layer and layered on the first sealing layer, and a wire electrically connected to the transistor, in which the wire includes a first portion covered with the first sealing layer and a second portion covered with the second sealing layer.

Semiconductor devices including electrically-isolated extensions and associated systems and methods are disclosed herein. An electrically-isolated extension may be coupled to a corresponding connection pad that is attached to a surface of a device. The electrically-isolated extensions may extend at least partially through one or more layers at or near the surface and toward a substrate or an inner portion thereof.

There is provided a semiconductor device including a semiconductor substrate, the semiconductor device including: a sensing portion that is provided on the semiconductor substrate and that is configured to detect predetermined physical information; a sensing pad portion that is provided above an upper surface of the semiconductor substrate and that is connected to the sensing portion; a gate runner which is provided above the upper surface of the semiconductor substrate and to which a gate potential is applied; and one or more separated conductive portions in which each separated conductive portion is provided between the sensing pad portion and the semiconductor substrate and that is separated from the gate runner.

In an embodiment an optoelectronic component includes a carrier having a mounting surface including a reflective coating, a semiconductor chip arranged on the carrier and a corrosion protection layer located on the semiconductor chip, the semiconductor chip being arranged in a vertical direction between the reflective coating and the corrosion protection layer, wherein the reflective coating includes a barrier layer disposed in the vertical direction in places between the semiconductor chip and the reflective coating, wherein the barrier layer includes an inorganic material and serves as an additional corrosion protection layer for the reflective coating, wherein the barrier layer has a vertical layer thickness between 1 nm and 100 nm, inclusive, and wherein the corrosion protection layer has a vertical layer thickness between 10 nm and 5000 nm, inclusive.

This disclosure relates to methods and compositions for treating a wafer having a pattern disposed on a surface of the wafer.

Provided is a silicone gel composition containing, as essential components: (A) an organopolysiloxane containing an alkenyl group bonded to two or more silicon atoms in one molecule, the organopolysiloxane comprising (a-1) a branched organopolysiloxane having an alkenyl group bonded to three or more silicon atoms only at an end of a molecular chain in one predetermined molecule, and (a-2) a linear organopolysiloxane having an alkenyl group bonded to two or more silicon atoms only at both ends of a molecular chain in one predetermined molecule; (B) a linear organohydrogenpolysiloxane containing hydrogen atoms bonded to two or more silicon atoms in one predetermined molecule; and (C) a platinum-based curing catalyst. Curing the silicone gel can provide a silicone gel cured product which has a degree of penetration of 40-100 as defined according to JIS K2220, has a free oil content of 15 mass % or less, has a low modulus and low stress, and does not exhibit oil bleeding over time.

A dually curable resin composition is provided. The composition comprises: (A) a first polyorganosiloxane comprising at least one alkenyl group and at least one alkoxy group in one molecule; (B) a second polyorganosiloxane comprising at least two photoreactive functional groups in one molecule on its side chain of siloxane backbone; (C) at least one silane compound represented by a particular chemical formula herein or its partially hydrolyzed compound; (D) at least one photoinitiator; and (E) at least one condensation reaction catalyst. A cured body prepared by curing the dually curable resin composition, and an electronic device comprising the cured body, are also provided.

The present disclosure relates to a light curable, light-heat or light-moisture dually curable, or light-heat-moisture multiple curable polyorganosiloxane composition, which has ease of synthesis, low volatile content, rapid curability, excellent toughness and/or superior optical/physical stability in a variety of fields such as coating materials, encapsulants, sealants and adhesives, a cured body obtained by curing said compositions, and an electronic device comprising the same.

A manufacturing method of a mounting structure, the method including: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member via bumps, the mounting member having a space between the first circuit member and the second circuit member; a step of preparing a sheet having a space maintaining layer; a disposing step of disposing the sheet on the mounting member such that the space maintaining layer faces the second circuit members; and a sealing step of pressing the sheet against the first circuit member and heating the sheet, to seal the second circuit members so as to maintain the space, and to cure the sheet. The bumps are solder bumps. The space maintaining layer after curing has a glass transition temperature of higher than 125° C., and a coefficient of thermal expansion at 125° C. or lower of 20 ppm/K or less.