Some embodiments of the disclosure provide an electronic device. The electronic device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer, and having a band gap greater than a band gap of the first nitride semiconductor layer; a group III-V dielectric layer disposed on the second nitride semiconductor layer; a gate electrode disposed on the second nitride semiconductor layer; and a first passivation layer disposed on the group III-V dielectric layer, wherein the group III-V dielectric layer is separated from the gate electrode by the first passivation layer.

Hotmelt silicone compositions are provided including: (A) a resinous alkenyl group-containing organopolysiloxane component, in which the silicon atom-bonded organic groups do not include an epoxy group-containing organic group, wherein the resinous alkenyl group-containing organopolysiloxane component includes (A-1) a resinous alkenyl group-containing organopolysiloxane including at least two alkenyl groups per molecule and free from a (Ar.sub.2SiO.sub.2/2) unit, and (A-2) a resinous alkenyl group-containing organopolysiloxane including at least two alkenyl groups per molecule and at least one (Ar.sub.2SiO.sub.2/2) unit; (B) an organohydrogenpolysiloxane having at least two silicon atom-bonded hydrogen atoms per molecule; and (C) a curing catalyst. The resinous alkenyl group-containing organopolysiloxane (A-1) is included in an amount of about 5 mass % or more based on the total mass of all the organopolysiloxane components in the hotmelt silicone composition.

The invention relates to the use as a coating or impregnating agent of an organosiloxane composition comprising a) 20 to 98.999989 wt % of at least one polyorganosiloxane comprising at least two alkenyl or alkynyl groups, as component A; b) 0.1 to 30 wt % of at least one linear or branched polyorganosiloxane comprising at least 3 Si—H groups, as component B; c) 0.000001 to 1 wt % of at least one UV-activatable, platinum-containing hydrosilylation catalyst, as component C; d) 0.00001 to 5 wt % of at least one alkynol of the general formula (I), where R.sup.1, R.sup.2 and R.sup.3 independently of one another are selected from H, C.sub.1-C.sub.6 alkyl and C.sub.3-C.sub.6 cycloalkyl; or R.sup.1 is selected from H, C.sub.1-C.sub.6 alkyl and C.sub.3-C.sub.6 cycloalkyl, and R.sup.2 and R.sup.3 are connected to one another and form a 3- to 8-membered ring, as component D; e) 0 to 79.899989 wt % of one or more polyorganosiloxanes comprising two terminal Si—H groups or one terminal Si—H group and one terminal alkenyl group, as component E; f) 0 to 20 wt % of one or more epoxy organosiloxanes, as component F; g) 0 to 5 wt % of one or more organosiloxanes, different from component A and having 1 to 5 Si atoms, and comprising at least two alkenyl groups, as component G; h) 0 to 79.899989 wt % of one or more silsesquioxanes, as component H; and i) 0 to 75 wt % of one or more additives, as component I; where the sum of components A to I is 100 wt %. ##STR00001##

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction.

A curable silicone composition of the present invention contains certain quantities of straight-chain organopolysiloxane which has at least two alkenyl groups and bound to silicon atoms and ≥0 mol % and <5 mol % of aryl groups per molecule, organopolysiloxane resin having at least two alkenyl groups bound to a silicon atom in the molecule, organohydrogenpolysiloxane resin which has a network molecular structure with at least two hydrogen atoms bound to a silicon atom per molecule, organohydrogenpolysiloxane resin which has a network molecular structure with at least two hydrogen atoms bound to a silicon atom per molecule, only at the end of the molecule, and hydrosilylation reaction catalyst, and (total mols of silicon-atoms-bound) hydrogen atoms/(total mols of silicon-atom-bound alkenyl groups) in the organopolysiloxane in the composition=1-3.

The present invention provides a joining that suppresses ion migration and also has excellent corrosion resistance, high bonding strength, and high reliability at the joining, and a semiconductor device. The present invention provides semiconductor joinings comprising: at least two semiconductor constituent members; and silver-containing bonding material layers that bond the semiconductor constituent members, in which a corrosion inhibitor coating layer is provided in contact with the silver-containing bonding material layers, and a semiconductor device including the same.

The package-on-package (POP) structure includes a first package unit of three-dimensional fan-out memory chips and a SiP package unit of the two-dimensional fan-out peripheral circuit chip. The first package unit includes: memory chips laminated in a stepped configuration; a molded substrate; wire bonding structures; a first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The SiP package unit includes: a second rewiring layer; a peripheral circuit chip; a third rewiring layer, bonded to the circuit chip; first metal connection pillars; a second encapsulating layer for the circuit chip and the first metal connection pillars; and second metal bumps on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer. Integrating the two package units into the POP is enabled by three rewiring layers and the molded substrate which supports the first package unit during wire bonding process.

A fan-out stacked semiconductor package structure and a packaging method thereof are disclosed. The structure includes a three-dimensional memory chip package unit and a two-dimensional fan-out peripheral circuit chip SiP package unit. The three-dimensional memory chip package unit includes: at least two memory chips laminated in a stepped configuration; a first rewiring layer; wire bonding structures, each of which being electrically connected to the bonding pad and the first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The two-dimensional fan-out peripheral circuit chip SiP package unit includes: a second rewiring layer; at least one peripheral circuit chip; a third rewiring layer, bonded to the peripheral circuit chip; metal connection pillars; a second encapsulating layer, encapsulating the peripheral circuit chip and the metal connection pillars; and second metal bumps, formed on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer.

A hermetically sealed semiconductor die package having a sidewall structure having a first opening and a second opening; a lid attached to the sidewall structure to hermetically seal the first opening; a substrate attached to the sidewall structure to hermetically seal the second opening, wherein the substrate comprises first, second, and third apertures; a first button attached to the substrate to hermetically seal the first aperture; a second button attached to the substrate to hermetically seal the second aperture; and a third button attached to the substrate to hermetically seal the third aperture.

A method of packaging an RF transistor device includes attaching one or more electronic devices to a carrier substrate, applying an encapsulant over at least one of the one or more electronic devices, and providing a protective structure on the carrier substrate over the one or more electronic devices. A packaged RF transistor device includes a carrier substrate, one or more electronic devices attached to the carrier substrate, an encapsulant material over at least one of the one or more electronic devices and extending onto the carrier substrate, and a protective structure on the carrier substrate over the one or more electronic devices and the encapsulant material.