A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.

A semiconductor package structure, including a lead frame, a die disposed on the front side of the lead frame, and a molding piece disposed on the lead frame and encapsulates the die, wherein the lead frame is provided with two extension portions extending respectively from two sides of the molding piece, and the extension portion is provided with recessed front surface and back surface on which a plating layer is formed.

In some examples, a semiconductor package comprises a semiconductor die; a conductive member coupled to the semiconductor die; and a wirebonded protrusion coupled to the conductive member. A physical structure of the wirebonded protrusion is determined at least in part by a sequence of movements of a wirebonding capillary used to form the wirebonded protrusion, the wirebonded protrusion including a ball bond and a bond wire, and the bond wire having a proximal end coupled to the ball bond. The bond wire has a distal end. The package also comprises a mold compound covering the semiconductor die, the conductive member, and the wirebonded protrusion. The distal end is in a common vertical plane with the ball bond and is not connected to a structure other than the mold compound.

A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include providing a carrier with a non-photosensitive protection layer, forming a pattern in the non-photosensitive protection layer, providing a semiconductor die with a contact pad on a first surface, and bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer. A second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer may be encapsulated with an encapsulant. The carrier may be removed leaving the non-photosensitive protection layer bonded to the semiconductor die. A redistribution layer may be formed on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface.

A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.

A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.

The present disclosure provides a semiconductor device and a preparation method thereof. The semiconductor device comprises: a semiconductor substrate; a passivation layer, arranged on an upper surface of the semiconductor substrate; a protective layer, arranged on an upper surface of the passivation layer, a dummy opening being formed on the protective layer; and, a dummy bump, partially located in the dummy opening and closely attached to the protective layer.

A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.

The present description relates to a method of manufacturing an interconnection structure of an integrated circuit intended to be encapsulated in an encapsulation resin in contact with a first surface of a protection layer. The protection layer is resting on a first surface of the interconnection structure. The interconnection structure comprising copper interconnection elements extending at least partly through an insulating layer and flush with the first surface of said interconnection structure. The manufacturing method includes a step of structuring of the protection layer or a step of forming of the protection layer with a structuring. The structuring step or the forming step is adapted to structuring the first surface of the protection layer in the form of an alternation of ridges and troughs.

A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.