Embodiments described herein may be related to apparatuses, processes, and techniques directed to a protective coating for an edge of a glass layer, in particular a glass core within a substrate of a package, where the protective coating serves to protect the edge of the glass core and fill in cracks at the edges of the glass. This protective coating will decrease cracking during stresses applied to the glass layer during manufacturing or operation. Other embodiments may be described and/or claimed.

The present disclosure relates to a semiconductor element, a manufacturing method of a semiconductor element, and an electronic apparatus, which enable suppression of crack occurrences and leaks. The present technology has a laminated structure including an insulating film having a CTE value between those of metal and Si and disposed under a metal wiring, and P—SiO (1 μm) having good coverage and disposed as a via inner insulating film in a TSV side wall portion. As the insulating film having a CTE that is in the middle between those of metal and Si, for example, SiOC is used with a thickness of 0.1 μm and 2 μm respectively in the via inner insulating film and a field top insulating film continuous to the via inner insulating film. The present disclosure can be applied to, for example, a solid-state imaging element used in an imaging device.

Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.

A semiconductor device including a first integrated circuit component, a second integrated circuit component, a third integrated circuit component, and a dielectric encapsulation is provided. The second integrated circuit component is stacked on and electrically coupled to the first integrated circuit component, and the third integrated circuit component is stacked on and electrically coupled to the second integrated circuit component. The dielectric encapsulation is disposed on the second integrated circuit component and laterally encapsulating the third integrated circuit component, where outer sidewalls of the dielectric encapsulation are substantially aligned with sidewalls of the first and second integrated circuit components. A manufacturing method of the above-mentioned semiconductor device is also provided.

A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.

A described example includes: an antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the antenna.

A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.

Provided is a sheet-like prepreg that has both a low coefficient of linear thermal expansion and high flexibility and offers excellent anti-warpage performance and cracking resistance. The sheet-like prepreg according to the present invention includes a curable composition and a sheet-like porous support impregnated with the curable composition. The sheet-like porous support is made from a material having a coefficient of linear thermal expansion of 10 ppm/K or less. The sheet-like prepreg gives a cured product having a glass transition temperature of −60° C. to 100° C. The curable composition includes one or more curable compounds (A) and at least one of a curing agent (B) and a curing catalyst (C). The curable compounds (A) include an epoxide having a weight per epoxy equivalent of 140 to 3000 g/eq in an amount of 50 weight percent or more of the totality of the curable compounds (A).

A package structure includes an insulating encapsulation, at least one die, and conductive structures. The at least one die is encapsulated in the insulating encapsulation. The conductive structures are located aside of the at least one die and surrounded by the insulating encapsulation, and at least one of the conductive structures is electrically connected to the at least one die. Each of the conductive structures has a first surface, a second surface opposite to the first surface and a slant sidewall connecting the first surface and the second surface, and each of the conductive structures has a top diameter greater than a bottom diameter thereof, and wherein each of the conductive structures has a plurality of pores distributed therein.