A semiconductor device includes a metal member, a first semiconductor chip, a second semiconductor chip, a first solder and a second solder. A quantity of heat generated in the first semiconductor chip is greater than the second semiconductor chip. The second semiconductor chip is formed of a material having larger Young's modulus than the first semiconductor chip. The first semiconductor chip has a first metal layer connected to the metal member through a first solder at a surface facing the metal member. The second semiconductor chip has a second metal layer connected to the metal member through a second solder at a surface facing the metal member. A thickness of the second solder is greater than a maximum thickness of the first solder at least at a portion of the second solder corresponding to a part of an outer peripheral edge of the second metal layer.

First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation layer extending exceeding edges the magnetic element. The isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding the edges of the magnetic element.

An electronic device and a method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing metal studs to further set a semiconductor die into the encapsulant.

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

A device includes a semiconductor die including a via, a layer of titanium tungsten (TiW) in contact with the via, and a copper pillar including a top portion and a bottom portion. The bottom portion is in contact with the layer of TiW. The copper pillar includes interdiffused zinc within the bottom portion.

A high voltage semiconductor package includes a semiconductor device. The semiconductor device includes a high voltage semiconductor transistor chip having a front side and a backside. A low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. A high voltage load electrode is disposed on the backside of the semiconductor transistor chip. The semiconductor package further includes a dielectric inorganic substrate. The dielectric inorganic substrate includes a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode, and at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode. The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and the dielectric inorganic substrate has a thickness of at least 50 μm.