According to the present invention, a power module that has a base to which a power semiconductor device is bonded and a sealing body for sealing said base and in which the base and the sealing body are bonded with a primer layer interposed therebetween, said primer layer being formed of a cured product of a silicone-modified polyimide resin composition containing, for example, components (A) to (E) below, has high reliability because delamination of an epoxy sealing resin under high temperature conditions is suppressed. (A) Silicone-modified polyimide resin represented by formula (1)
Ee-Ff-Gg  (1)
E is represented by formula (2), F is represented by formula (3), G is a divalent group derived from diamine, f+e+g=100 mol %, the molar ratio f/(e+g) is 0.9-1.1, and e is 1-90 when the sum of e and g is 100. ##STR00001##
R.sup.A is a divalent hydrocarbon group, R.sup.1 and R.sup.2 are alkyl groups, R.sup.3 and R.sup.4 are monovalent aliphatic hydrocarbon groups, R.sup.5 and R.sup.6 are aryl groups or the like, m is an integer of 0-20, n is an integer of 1-20, o is an integer of 0-20, and m+n+o is an integer of 1-30.
-Im-X-Im-  (3)
Im is a cyclic group including a cyclic imide structure, and X is a single bond or the like. (Bc) Heat-decomposable radical initiator (C) Solvent (D) Antioxidant (E) Fumed silica.

A method of manufacturing semiconductor devices, such as integrated circuits includes arranging one or more semiconductor dice on a support surface. Laser direct structuring material is molded onto the support surface having the semiconductor die/dice arranged thereon. Laser beam processing is performed on the laser direct structuring material molded onto the support surface having the semiconductor die/dice arranged thereon to provide electrically conductive formations for the semiconductor die/dice arranged on the support surface. The semiconductor die/dice provided with the electrically-conductive formations are separated from the support surface.

A component carrier includes a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure; a barrier structure; and a component. The component has at least one pad embedded in the stack and/or in the barrier structure. At least a portion of one of the electrically conductive layer structure and the at least one pad includes copper in contact with the barrier structure.

A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

An electronic package is provided. The electronic package includes an amplifier component, a control component, and a first circuit layer. The control component is disposed above the amplifier component. The first circuit layer is disposed between the amplifier component and the control component. The control component is configured to transmit a first signal to the amplifier component and to output a second signal amplified by the amplifier component.

An electronic package and a method of manufacturing an electronic package are provided. The electronic package includes a carrier, an antenna substrate, and an electronic component. The carrier has a first surface and a second surface. The antenna substrate includes a resonant cavity and is disposed over the first surface. The antenna substrate is closer to the first surface than the second surface of the carrier. The electronic component is disposed between the antenna substrate and the second surface of the carrier.

A semiconductor package includes a substrate, a preformed feeding element, a preformed shielding element, and an encapsulant. The preformed feeding element is disposed on the substrate and the preformed feeding element is disposed on the substrate and adjacent to the preformed feeding element. The encapsulant encapsulates the preformed feeding element and the preformed shielding element.

A processor substrate includes: an electrically insulating material having a first main side and a second main side opposite the first main side; a plurality of electrically conductive structures embedded in the electrically insulating material and configured to provide an electrical interface at the first main side of the electrically insulating material and to provide electrical connections from the electrical interface to the second main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material and which exceeds a voltage limit of the processor substrate to a voltage that is below the voltage limit of the processor substrate. An electronic system that includes the processor substrate is also described.

An electronic package structure is provided. The electronic package structure includes a first carrier, a first electronic component, a first optical channel, and a second electronic component. The first electronic component is disposed on or within the first carrier. The first optical channel is disposed within the first carrier. The first optical channel is configured to provide optical communication between the first electronic component and the second electronic component. The first carrier is configured to electrically connect the first electronic component.

An electrical package can include a substrate having a first side and a second side opposite the first side. One or more electrical components mounted to the substrate, and a plurality of electrically conductive interconnect members can be coupled to the second side of the substrate. At least one of the interconnect members can have an elongated shape with a length that is longer than a width. The interconnect member with the elongated shape positioned can be at or proximate one of the corners. The interconnect members can be arranged as a grid, with first interconnect members each occupying a single grid cell, and second interconnect members each occupying at least two grid cells. The second interconnect members can have a shape of two of the first interconnect members coupled by a bridge portion.