A manufacturing method of a mounting structure includes: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member; a disposing step of disposing a thermosetting sheet and a thermoplastic sheet on the mounting member, with the thermosetting sheet interposed between the thermoplastic sheet and the first circuit member; a first sealing step of pressing a stack of the thermosetting sheet and the thermoplastic sheet against the first circuit member, and heating the stack, to seal the second circuit members and to cure the thermosetting sheet into a cured layer; and a removal step of removing the thermoplastic sheet from the cured layer. At least one of the second circuit members is a hollow member having a space from the first circuit member, and in the first sealing step, the second circuit members are sealed so as to maintain the space.

A lead frame is provided, including one or more power terminals and one or more control terminals, wherein at least one of the control terminals is externally terminated with a press-fit contact member, and wherein at least one of the control terminals and at least one power terminals are formed from different materials. With the disclosed lead frame of the invention, lower material cross sections in the power terminals will be provided because of the better electrical conductivity when using pure copper compared to alloys with higher mechanical strengths. Also specific/different plating could be added to the individual needs of the different pin types without using masks in the plating process.

A thin, flexible computerized sensing platform which can be affixed to a structure to be sensed, which has excellent mechanical coupling between the sensors and the object to be sensed, which can be self-powered and rechargeable, and which can be environmentally sealed, and a method for assembling and utilizing the same.

Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.

According to one embodiment, an electromagnetic wave attenuator includes a first structure body. The first structure body includes a first member, a second member, and a third member. The first member includes a first magnetic layer and a first nonmagnetic layer alternately provided in a first direction. The first nonmagnetic layer is conductive. The first direction is a stacking direction. The second member includes a second magnetic layer and a second nonmagnetic layer alternately provided in the first direction. The second nonmagnetic layer is conductive. The third member includes a third nonmagnetic layer. The third nonmagnetic layer is conductive. A direction from the third member toward the first member is along the first direction. A direction from the third member toward the second member is along the first direction. A first magnetic layer thickness is greater than a second magnetic layer thickness.

A semiconductor device has a substrate, a first circuit, a first inductor, a second circuit and a second inductor IND2. The substrate includes a first region and a second region, which are regions different from each other. The first circuit is formed on the first region. The first inductor is electrically connected with the first circuit. The second circuit is formed on the second regions. The second inductor is electrically connected with the second circuit and formed to face the first inductor. A penetrating portion is formed in the substrate. The penetrating portion is formed such that the penetrating portion surrounds one or both of the first circuit and the second circuit in plan view.

The semiconductor device includes a semiconductor element, a first lead, and a second lead. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a thickness direction. The semiconductor element includes an electron transit layer disposed between the element obverse surface and the element reverse surface and formed of a nitride semiconductor, a first electrode disposed on the element obverse surface, and a second electrode disposed on the element reverse surface and electrically connected to the first electrode. The semiconductor element is mounted on the first lead, and the second electrode is joined to the first lead. The second lead is electrically connected to the first electrode. The semiconductor element is a transistor. The second lead is spaced apart from the first lead and is configured such that a main current to be subjected to switching flows therethrough.

The technology of this application relates to a semiconductor packaged structure, including a circuit board, a chip, a pin, and a plastic package body. The pin includes a connecting part and a pressfit, one end of the connecting part is welded to the circuit board, the other end is flush with a top surface of the plastic package body, the connecting part has a mounting hole, the pressfit is disposed in the mounting hole and is in an interference fit with the connecting part, the pressfit is exposed from the top surface of the plastic package body. Alternatively, the pin includes a pressfit, the plastic package body is provided with a mounting hole that runs through a plastic package body, the pressfit is provided in the mounting hole, one end of the pressfit is welded to the circuit board, the other end is exposed from the top surface of the plastic package body.

A semiconductor chip includes a front surface and a back surface, a source pad, a drain pad and a gate pad on the front surface; a die pad under the semiconductor chip and bonded to the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin. A plurality of vias for external connection are formed to connect to the source pad. A first subset of the plurality of vias for external connection is disposed along a first side of the source pad, and a second subset of the plurality of vias for external connection is disposed along a second side of the source pad, wherein the first and second sides are arranged adjacent to each other to form a first edge of the source pad.

Disclosed are a packaging substrate, a grid array package, and a preparation method therefor. The packaging substrate comprises a plurality of packaging units, and each packaging unit is defined by a closed packaging line. The packaging substrate comprises: a base substrate having a first surface and a second surface that are opposite to each other, a plurality of solder pads provided on the first surface, and a metal layer provided on the second surface. In a given packaging unit, the metal layer comprises a plurality of lead pads, at least one lead pad extending from an inner side of the packaging unit defined by the packaging line to an outer side. The lead pad is connected to one solder pad by means of a connecting member penetrating through the base substrate, and an orthographic projection of the connecting member on the base substrate at least partially covers the packaging line.