A semiconductor package includes: a first substrate; a semiconductor chip mounted on the first substrate such that a circuit formation surface is oriented toward the first substrate; a second substrate arranged above the first substrate, the semiconductor chip being sandwiched between the first substrate and the second substrate; and a resin that seals the semiconductor chip and that is filled between the first substrate and the second substrate, wherein the second substrate includes a solder resist layer having a first surface facing a back surface that is an opposite surface of the circuit formation surface of the semiconductor chip, and wherein on an area of the first surface of the solder resist layer facing the back surface of the semiconductor chip, at least one protruding portion that protrudes towards the back surface of the semiconductor chip is provided.

A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the t least one side surface. The first adhesive layer and the first resin layer contact each other.

A technique capable of shortening process time for plasma cleaning is provided. A method of manufacturing a semiconductor device includes a step of preparing a substrate including a plurality of device regions each including a semiconductor chip electrically connected to a plurality of terminals formed on a main surface by a wire, a step of delivering the substrate while emitting plasma generated in atmospheric pressure to the main surface of the substrate, a step of delivering the substrate while capturing an image of a region of the main surface of the substrate and a step of forming a sealing body by sealing the semiconductor chip and the wire with a resin.

A semiconductor device having an integrated antenna is provided. The semiconductor device includes a base die having an integrated circuit formed at an active surface and a cap die bonded to the backside surface of the base die. A metal trace is formed over a top surface of the cap die. A cavity is formed under the metal trace. A conductive via is formed through the base die and the cap die interconnecting the metal trace and a conductive trace of the integrated circuit.

A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

An electronic component includes a mounting substrate, and first and second devices each including a functional element. The first device is spaced apart from and faces the mounting substrate. The second device is located on the mounting substrate and faces the first device. A functional element of the first device is located on a first surface facing the second device, in the first device. A functional element of the second device is located on a second surface facing the first device, in the second device.

The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.

This application discloses a package structure and a package system. The package structure may be used for packaging various types of chips, and is coupled to a PCB, so as to form the package system. The package structure includes a package base layer, a chip, a package body, and a connecting assembly. The package base layer has a first surface and a second surface that are opposite to each other. The chip is coupled to the first surface, and there is a chip pad on a surface that is of the chip and that is away from the package base layer. The package body covers the package base layer and the chip to protect the structure, and the chip pad is wired to a surface of the package body through the connecting assembly.

The present disclosure provides an electronic apparatus including a first surface, a second surface, a third surface, a plurality of conductive elements, and an encapsulant. The second surface is nonparallel to the first surface. The third surface is distinct from the first surface and the second surface. The plurality of conductive elements are exposed from the second surface. The encapsulant covers the third surface and exposes the first surface and the second surface.

A method includes forming a plurality of first conductive vias over a redistribution layer (RDL); disposing a first die over the RDL and adjacent to the first vias; and forming a plurality of second conductive vias over and electrically connected to the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias. The method further includes forming a plurality of third conductive vias over the first die; disposing a second die over the first die and adjacent to the third conductive vias; and encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias with a molding material.