Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

An integrated circuit includes a lead frame, a first die, and a second die. The first die is bonded to and electrically connected to the lead frame. The second die is electrically connected to and spaced apart from the first die.

Disclosed is a packaging method for circuit units, wherein the circuit units comprise a silicon layer substrate and a silicon dioxide layer overlaid on the silicon layer substrate. The packaging method for a circuit unit comprises: attaching a plurality of circuit units to a circuit baseplate in a spaced and inverted mode, wherein the silicon dioxide layer is attached to the circuit baseplate, and the silicon layer substrate faces away from the circuit baseplate; forming an insulator between the circuit units; removing the silicon layer substrate to expose the silicon dioxide layer; and forming an electromagnetic shielding layer on the silicon dioxide layer and the insulator.

Disclosed is a packaging structure for circuit units, comprising: a circuit baseplate, wherein the circuit baseplate is provided thereon with a circuit unit, the circuit unit including a silicon dioxide layer and an electronic device arranged on the silicon dioxide layer; an insulator, wherein the insulator surrounds the circuit unit; and an electromagnetic shielding layer, wherein the electromagnetic shielding layer covers the circuit unit and the insulator.

A package structure is provided. The package structure includes a redistribution structure and a semiconductor die over the redistribution structure, and bonding elements below the redistribution structure. The semiconductor die has a first sidewall and a second sidewall connected to each other. The bonding elements include a first row of bonding elements and a second row of bonding elements. In a plan view, the second row of bonding elements is arranged between the first row of bonding elements and an extending line of the second sidewall. A minimum distance between the second row of bonding elements and the first sidewall is greater than the minimum distance between the first row of bonding elements and the first sidewall.

A package structure is provided. The package structure includes a first conductive pad in an insulating layer, a first under bump metallurgy structure under the first insulating layer, and a first conductive via in the insulating layer. The first conductive via is vertically connected to the first conductive pad and the first under bump metallurgy structure. In a plan view, a first area of the first under bump metallurgy structure is confined within a second area of the first conductive pad.

A package structure is provided. The package structure includes a redistribution structure and a first semiconductor die over the redistribution structure. The package structure also includes a wall structure laterally surrounding the first semiconductor die and the wall structure includes a plurality of partitions separated from one another. The package structure also includes an underfill material between the wall structure and the first semiconductor die. The package structure also includes a molding compound encapsulating the wall structure and the underfill material.

A chip package structure includes at least one semiconductor die attached to a redistribution structure, a first underfill material portion located between the redistribution structure and the at least one semiconductor die and laterally surrounding the solder material portions, a molding compound laterally surrounding at least one semiconductor die, and a second underfill material portion contacting sidewalls of the redistribution structure and sidewalls of the molding compound and including at least one cut region. The second underfill material portion includes a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.

A semiconductor package includes: a package substrate; a semiconductor chip mounted above the package substrate; a chip connection terminal interposed between the semiconductor chip and the package substrate; an adhesive layer disposed on the package substrate and that covers a side and a top surface of the semiconductor chip and surrounds the chip connection terminal between the semiconductor chip and the package substrate; a molding layer disposed on the package substrate and that surrounds the adhesive layer; an interposer mounted on the adhesive layer and the molding layer, where the interposer includes an interposer substrate; and a conductive pillar disposed on the package substrate, where the conductive pillar surrounds the side of the semiconductor substrate, penetrates the molding layer in a vertical direction and connects the package substrate to the interposer substrate.

A semiconductor device includes a substrate, a package structure, a thermal interface material (TIM) layer, and a lid structure. The package structure is disposed on the substrate. The TIM layer is disposed on the package structure. The TIM layer includes a liquid state metal material. The lid structure is disposed on the substrate and the TIM layer. The lid structure includes a trench facing the package structure. At least a portion of the TIM layer is located in the trench.