A semiconductor packaging structure includes a substrate, a wiring layer, a mask layer, and a sealing layer. The substrate has an effective region and a dummy region surrounding the effective region. The wiring layer is disposed on the effective and dummy regions, and is formed with a predetermined pattern including spaced-apart protrusions to define at least one cavity partially exposing the dummy region. The mask layer covers the wiring layer, and is formed with a through hole to communicate in space with the cavity. The through hole is smaller in size than the cavity, and cooperates with the cavity to form an accommodating space. The sealing layer covers the mask layer, and includes an engaging element filling the accommodating space and adhering to the substrate.

A semiconductor device includes an insulated circuit board having a conductive pattern layer, a sintered member disposed on the conductive pattern layer, a semiconductor chip placed on the sintered member, and a coating material covering the semiconductor chip. The sintered member has, on a surface thereof opposite to the conductive pattern layer, a frame shaping the outer edge of a recess. The semiconductor chip is mounted in the recess such that its top face is located closer to the conductive pattern layer than a top end of the frame.

A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the semiconductor chip and the dummy chip in the direction perpendicular to the first surface of the substrate, an upper end of the extension portion being disposed to be lower than the upper surface of the semiconductor chip; and a sealing material disposed on the first surface of the substrate, and sealing the semiconductor chip and the dummy chip.

A semiconductor device includes a first die, a second die, a first redistribution layer (RDL) structure and a connector. The RDL structure is disposed between the first die and the second die and is electrically connected to the first die and the second die and includes a first polymer layer, a second polymer layer, a first conductive pattern and an adhesion promoter layer. The adhesion promoter layer is between and in direct contact with the second polymer layer and the first conductive pattern. The connector is disposed in the first polymer layer and in direct contact with the second die and the first conductive pattern.

A semiconductor structure may be provided, including a conductive pad, a slot arranged through the conductive pad, a passivation layer arranged over the conductive pad and a plurality of electrical interconnects arranged under the conductive pad. The conductive pad may include an electrically conductive material and the slot may include an electrically insulating material. The passivation layer may include an opening that may expose a portion of the conductive pad and the slot may be arranged laterally between the exposed portion of the conductive pad and the plurality of electrical interconnects.

A semiconductor package assembly and method of manufacturing is provided. The assembly includes a semiconductor package and a moulding resin case encapsulating the semiconductor package. The package includes a lead frame having a first frame side and a second frame side opposite to the first frame side; a silicon die structure having a first die side and a second die side opposite to the first side, the silicon die structure being mounted with its second die side on the first frame side of the lead frame; one or more bond wires electrically connecting the silicon die structure with the lead frame; as well as a coating layer covering the semiconductor package from the encapsulating moulding resin case, the coating layer being composed of two or more different amorphous layer coatings. The use of a coating layer covering the complete semiconductor package forming the encapsulating moulding resin case prevents any corrosion.

A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.

This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.

A method for producing a semiconductor device includes dicing, at a scribe area of a semiconductor wafer, the semiconductor wafer into semiconductor chips including respective circuit areas formed on the semiconductor wafer, the scribe area being provided between the circuit areas and extending in a first direction in a plan view, wherein the scribe area includes a first area extending in the first direction and second areas including monitor pads and extending in the first direction and located on both sides of the first area, wherein the method includes removing at least portions of the monitor pads by emitting laser beam to the second areas before the dicing, and wherein, in the dicing, the semiconductor wafer is diced at the first area.

Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy wafer, and forming a molding layer and a mold covering layer. A second semiconductor die may be stacked on the first semiconductor die and a photosensitive dielectric layer may be formed. Conductive vias penetrating the photosensitive dielectric layer may be plated.