A semiconductor package structure includes a circuit pattern structure, an encapsulant and an anchoring structure. The encapsulant is disposed on the circuit pattern structure. The anchoring structure is disposed adjacent to an interface between the encapsulant and the circuit pattern structure, and is configured to reduce a difference between a variation of expansion of the encapsulant and a variation of expansion of the circuit pattern structure in an environment of temperature variation.

A semiconductor device includes a semiconductor chip having a terminal thereon, a lead frame for connection to an external device, a bonding wire connecting the terminal of the semiconductor chip and the lead frame. A mold resin layer encloses the semiconductor chip and the bonding wire, such that a portion of the lead frame extends out of the mold resin layer. A molecular bonding layer has a portion on a surface of the bonding wire and includes a first molecular portion covalently bonded to a material of the bonding wire and a material of the mold resin layer.

A semiconductor module includes: a semiconductor element; a first lead frame including a first portion on which the semiconductor element is mounted; a sealing member sealing the semiconductor element and the first portion; and a heat dissipation member which is integrated with the sealing member and dissipates heat generated in the semiconductor element. The heat dissipation member is insulated from the semiconductor element and the first portion by the sealing member. Therefore, the semiconductor module that is applicable to vertical semiconductor elements and ensures electrical insulation between the semiconductor element and the heat dissipation member when implementing the semiconductor module onto a circuit board, can be provided.

A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.

An electronic device includes a first molded product integrated with an electronic component, and a second molded product secondarily molded outside of the first molded product. The first molded product includes a thermosetting resin, and a first additive contained in the thermosetting resin, and the second molded product includes a thermoplastic resin, and a second additive contained in the thermoplastic resin and having a reactive group that chemically bonds with the first additive. At an interface between the first molded product and the second molded product, the first additive and the second additive are joined to each other by one or more joint actions selected from covalent bonding, ionic bonding, hydrogen bonding, intermolecular forces, dispersion force, and diffusion. As a result, the adhesion between both the molded products can be firmly secured through the molding technique such as the transfer molding method or the compression molding method.

An integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, a row of discrete devices disposed laterally with respect to the integrated circuit die, and encapsulant mechanically coupling the redistribution layer, integrated circuit die, and the row of discrete devices. In at least one embodiment, the row of discrete devices is a row of decoupling capacitors disposed proximate to the integrated circuit die and coupled to the integrated circuit die and a power distribution network. In at least one embodiment, a second integrated circuit die is disposed above the redistribution layer and disposed laterally with respect to the integrated circuit die and the row of discrete devices. The second integrated circuit die is mechanically coupled to the redistribution layer, integrated circuit die, and the row of discrete devices and is partially surrounded by the row of discrete devices.

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.

The present invention concerns a method for forming a metal layer for electromagnetic shielding and thermal management of active components, preferably by wet chemical metal plating, using an adhesion promotion layer on the layer of molding compound and forming at least one metal layer on the adhesion promotion layer or forming at least one metal layer on the adhesion promotion layer by wet chemical metal plating processes.

Provided is a sealing sheet capable of preventing void and filler segregation from occurring when forming a sealing body in which semiconductor chips are buried in the sealing sheet. The sealing sheet has a viscosity within the range of 1 Pa.Math.s to 50000 Pa.Math.s at 90° C.