Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

A package structure includes a metal member and a resin member. The metal member has an obverse surface facing one side in a first direction. The resin member is disposed in contact with at least a portion of the obverse surface. The obverse surface has a roughened area. The roughened area includes a plurality of first trenches recessed from the obverse surface, each of the first trenches having a surface with a greater roughness than the obverse surface. The plurality of first trenches extend in a second direction perpendicular to the first direction and are next to each other in a third direction perpendicular to the first direction and the second direction. The plurality of first trenches are filled up with the resin member.

A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.

According to one embodiment, a ceramic metal circuit board is a ceramic metal circuit board formed by bonding metal circuit plates to at least one surface of a ceramic substrate. At least one of the metal circuit plates has an area of not less than 100 mm.sup.2 and includes a concave portion having a depth of not less than 0.02 mm within a range of 1% to 70% of a surface of the at least one of the metal circuit plates. The concave portion is provided not less than 3 mm inside from an end of the metal circuit plate.

A package structure and method of forming the same are provided. The package structure includes a die, a via, an encapsulant, an adhesion promoter layer, and a polymer layer. The via is laterally aside the die. The encapsulant laterally encapsulates the die and the via. The adhesion promoter layer is sandwiched between the via and the encapsulant. The encapsulant comprises a portion aside the via and under the adhesion promoter layer, and the portion of the encapsulant is sandwiched between the adhesion promoter layer and the polymer layer.

In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

In some examples, a semiconductor package comprises a semiconductor die; a conductive member coupled to the semiconductor die; and a wirebonded protrusion coupled to the conductive member. A physical structure of the wirebonded protrusion is determined at least in part by a sequence of movements of a wirebonding capillary used to form the wirebonded protrusion, the wirebonded protrusion including a ball bond and a bond wire, and the bond wire having a proximal end coupled to the ball bond. The bond wire has a distal end. The package also comprises a mold compound covering the semiconductor die, the conductive member, and the wirebonded protrusion. The distal end is in a common vertical plane with the ball bond and is not connected to a structure other than the mold compound.

The present description relates to a method of manufacturing an interconnection structure of an integrated circuit intended to be encapsulated in an encapsulation resin in contact with a first surface of a protection layer. The protection layer is resting on a first surface of the interconnection structure. The interconnection structure comprising copper interconnection elements extending at least partly through an insulating layer and flush with the first surface of said interconnection structure. The manufacturing method includes a step of structuring of the protection layer or a step of forming of the protection layer with a structuring. The structuring step or the forming step is adapted to structuring the first surface of the protection layer in the form of an alternation of ridges and troughs.

An integrated circuit that includes micro-etched channels on a bottom surface is provided. The integrated circuit includes a lead frame having electrically conductive contact terminal pads and a die centrally disposed in the lead frame. Wire bonds provide an electrical connection from the die to the electrically conductive contact terminal pads. A mold compound encapsulates the die and the wire bonds, where a bottom surface of the mold compound is flush with a bottom surface of the contact terminal pads. A channel is defined in the bottom surface of the mold compound around a periphery of the contact terminal pads.

A semiconductor device includes a semiconductor element, a support member, and a bonding layer interposed between the semiconductor element and the support member, wherein the bonding layer contains an alloy of first metal and second metal.