A semiconductor device includes a semiconductor chip including a chip substrate and a MEMS element, wherein the chip substrate includes a first surface and a second surface arranged opposite to the first surface, and wherein the MEMS element is disposed at the first surface of the chip substrate and the MEMS element includes a sensitive area; at least one electrical interconnect structure electrically connected to the first surface of the chip substrate; a chip carrier electrically connected to the at least one electrical interconnect structure; a flexible film provided over the second surface of the chip substrate to form a pocket in which the semiconductor chip resides; and a compressible material arranged between the second surface of the chip substrate and the flexible film.

An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.

In examples, a sensor package includes a semiconductor die, a sensor on the semiconductor die, and a mold compound covering the semiconductor die. The mold compound includes a sensor cavity over the sensor. The sensor package includes a polymer film member on the sensor and circumscribed by a wall of the mold compound forming the sensor cavity. The polymer film member is exposed to an exterior environment of the sensor package.

Electronic module (1) including an encapsulation (20), a carrier substrate (10) enclosed by the encapsulation (20) and having a component side (25) which has a first metallization layer (15) and on which at least one first electronic component (30) is arranged, wherein at least one second metallization layer (35) for at least one second electronic component (31), in particular for controlling the first electronic component (30), is provided on an outer side (A) of the encapsulation (2), wherein the encapsulation (20) has at least one plated-through hole (5) for electrical connection, in particular for direct electrical connection, of the first electronic component (30) and the second electronic component (31).

A surface acoustic wave (SAW) filter package structure includes a dielectric substrate having a dielectric layer, a first patterned conductive layer, a second patterned conductive layer, and a conductive connection layer. The conductive connection layer is electrically connected between the first patterned conductive layer and the second patterned conductive layer, which are disposed at opposite sides of the dielectric layer. The second patterned conductive layer has a finger electrode portion. An active surface of a chip is faced toward the finger electrode portion. A polymer sealing frame is disposed between the chip and the dielectric substrate and surrounds the periphery of the chip to form a chamber together with the chip and the dielectric substrate. The mold sealing layer is disposed on the dielectric substrate and covers the chip and the polymer sealing frame. A manufacturing method of the SAW filter package structure is also disclosed.

A method for packaging semiconductor dies by overmolding is disclosed. The dies are embedded in a substrate of a mold material, and cavities are produced in the mold substrate by producing 3D structures of a sacrificial material prior to the overmolding step. Afterwards, the sacrificial material is removed to thereby create cavities in the mold substrate. A conformal layer is produced on the 3D structures prior to overmolding, and the mold substrate is thinned to expose an upper surface of the 3D structures. The conformal layer is not removed when the sacrificial structures are removed. In this way, the conformal layer remains on the surfaces of the mold substrate inside the cavity. In one aspect, the conformal layer may have a protective function, useful in the production of packages including dies which come into contact with fluid substances.

Terahertz device A1 includes first resin layer 21, columnar conductor 31, wiring layer 32, terahertz element 11, second resin layer 22, and external electrode 40. Resin layer 21 includes first resin layer obverse face 211 and first resin layer reverse face 212. Columnar conductor 31 includes first conductor obverse face 311 and first conductor reverse face 312, penetrating first resin layer 21 in z-direction. Wiring layer 32 spans between first resin layer obverse face 221 and first conductor obverse face 311. Terahertz element 11 includes element obverse face 111 and element reverse face 112, and converts between terahertz wave and electric energy. Second resin layer 22 includes second resin layer obverse face 221 and second resin layer reverse face 222, and covers wiring layer 32 and terahertz element 11. External electrode 40, disposed offset in a direction first resin layer reverse face 222 faces with respect to first resin layer 32, is electrically connected to columnar conductor 31. Terahertz element 11 is conductively bonded to wiring layer 32.

An electronic device with stud bumps is disclosed. In an embodiment an electronic device includes a carrier board having an upper surface and an electronic chip mounted on the upper surface, the electronic chip having a mounting side facing the upper surface of the carrier board, a top side facing away from the upper surface, and sidewalls connecting the mounting side to the top side, wherein the electronic chip has equal to or less than 5 stud bumps per square millimeter of a base area of the mounting side, wherein the carrier board has at least one recess in the upper surface, and wherein at least one of the stud bumps reaches into the recess.

A semiconductor device includes: a semiconductor layer including a channel layer; a contact region provided at a predetermined size in a thickness direction of the semiconductor layer, and having an impurity concentration that is higher than an impurity concentration of the surrounding semiconductor layer; a gate electrode facing the channel layer, and provided on the semiconductor layer and spaced from the contact region; and an electrode that is in contact with the semiconductor layer and electrically coupled to the channel layer via the contact region, and extending more on at least the gate electrode side than the contact region.

A semiconductor device according to the disclosure includes a first semiconductor chip, a second semiconductor chip, a first metal plate provided on an upper surface of the first semiconductor chip, a second metal plate provided on an upper surface of the second semiconductor chip and a sealing resin covering the first semiconductor chip, the second semiconductor chip, the first metal plate and the second metal plate, wherein a groove is formed in the sealing resin, the groove extending downwards from an upper surface of the sealing resin, the first metal plate includes, at an end facing the second metal plate, a first exposed portion exposed from a side face of the sealing resin forming the groove, and the second metal plate includes, at an end facing the first metal plate, a second exposed portion exposed from a side face of the sealing resin forming the groove.