A semiconductor package structure is provided. The semiconductor package structure includes a redistribution layer (RDL) structure formed on a non-active surface of a semiconductor die. An antenna structure includes a first antenna element formed in the RDL structure, a first insulating layer covering the RDL structure, a second insulating layer formed on the first insulating layer, and a second antenna element formed on and in direct contact with the second insulating layer.

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

An electronic component package of an embodiment of the disclosure includes a base, a first plated layer, a first electronic component chip, a second plated layer, and a second electronic component chip. The base includes a first surface and a second surface. The first plated layer covers the first surface. The first electronic component chip is provided on the first plated layer with a first insulating layer being interposed therebetween. The second plated layer covers the second surface. The second electronic component chip is provided on the second plated layer with a second insulating layer being interposed therebetween. The first plated layer and the second plated layer each include a first metal material that is less likely to undergo an ion migration phenomenon than silver (Ag).

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

An electronic device includes a semiconductor die, a bond wire coupled to a side of the semiconductor die, and a package structure that encloses the semiconductor die and the bond wire. The package structure has a package side with a recess that extends inward from the package side toward the side of the semiconductor die. The recess has a bottom that is spaced apart from the side of the semiconductor die, and the bottom is spaced apart from the bond wire.

A semiconductor package includes a first interconnection structure, a first semiconductor chip on the first interconnection structure, an encapsulant covering the first semiconductor chip, a second interconnection structure disposed on the first semiconductor chip and the encapsulant, including a plurality of interconnection layers, and having an opening having a step portion, exposing a portion of an upper surface of at least one of the plurality of interconnection layers, and a heat dissipation pattern disposed in the opening, passing through the encapsulant and in contact with at least a portion of an upper surface of the first semiconductor chip, and including a material having a thermal conductivity higher than thermal conductivity of silicon (Si). The heat dissipation pattern includes a lower portion having a first width, and an upper portion disposed on the lower portion and having a second width greater than the first width, and the upper portion of the heat dissipation pattern is in contact with the exposed portion of the upper surface of the at least one interconnection layer.

A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact.

Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.

An RFIC device including a resin block having a first surface, a second surface that faces the first surface, and a through-hole that extends through the first surface and the second surface. Moreover, the RFIC device includes an RFIC element that is embedded in the resin block and a coil antenna disposed in the resin block that is connected with the RFIC element and that has a central axis that extends from the first surface to the second surface. In addition, the through-hole extends inside the coil antenna.

Each of a plurality of semiconductor elements included in a semiconductor package includes a front-surface electrode being provided on a semiconductor substrate on a side opposite to a conductor substrate, a back-surface electrode being joined to the conductor substrate, a control pad configured to control current flowing between the front-surface electrode and the back-surface electrode, a frame being electrically connected to the front-surface electrode, a portion of the frame being exposed from a surface of a sealing material from which a lower surface of the conductor substrate is exposed, and a plurality of terminal blocks being electrically connected to a plurality of first pads, a portion of the plurality of terminal blocks being exposed from a surface of the sealing material, the surface being provided on a side opposite to the surface of the sealing material from which the lower surface of the conductor substrate is exposed.