A semiconductor package including a package base substrate, an interposer on the package base substrate, a plurality of semiconductor chips on the interposer, and a stiffener structure including a stiffener frame and a stiffener extension portion, the stiffener frame being on the package base substrate and apart from the interposer, the stiffener extension portion extending from the stiffener frame, spaced apart from the plurality of semiconductor chips, and extending onto the interposer to have a portion on the interposer, and the stiffener frame being an integral structure with the extension portion, may be provided.

Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

A thermally conductive and electrically insulating substrate is provided. The thermally conductive and electrically insulating substrate includes a thermally conductive base, an electrically insulating layer, and one or more metal sheets. The electrically insulating layer is disposed on the thermally conductive base, and the one or more metal sheets are disposed on the electrically insulating layer. The metal sheet is allowed to have one or more chips arranged thereon, and a surface of the metal sheet where the metal sheet is allowed to be engaged with the chip is not parallel to a surface of the electrically insulating layer where the electrically insulating layer is mated with the metal sheet.

A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

A package structure with a wettable side surface and a manufacturing method thereof, and a vertical package module are disclosed. The package structure includes a first dielectric layer, a chip and a circuit layer. The first dielectric layer is provided with a package cavity, side wall bonding pads are arranged on a side wall of the first dielectric layer and located outside the package cavity. The chip is packaged inside the package cavity, pins of the chip face first surface of the first dielectric layer. The circuit layer is arranged on the first surface of the first dielectric layer, and the circuit layer is directly or indirectly connected to the side wall bonding pads and the pins of the chip.

A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

A semiconductor device including an interposer including a central region and an edge region entirely surrounding the central region, wherein the interposer includes a wiring structure disposed in the first region and a metal structure disposed continuously within the entirety of the second region, a first semiconductor chip mounted in the central region and connected to the wiring structure, and a second semiconductor chip mounted in the central region adjacent to the first semiconductor chip and connected to the second wiring structure.

An integrated circuit assembly may include an integrated circuit having a plurality of programmable logic sectors and an interposer circuit positioned adjacent to the integrated circuit. The interposer circuit may include at least one voltage regulator that distributes a voltage to at least one of the plurality of programmable logic sectors and at least one thermal sensor that measures a temperature of the at least one of the plurality of programmable logic sectors.

This document describes a passive thermal-control system that can be integrated into an electronic speaker device and associated electronic speaker devices. The passive thermal-control system uses an architecture that combines heat spreaders and thermal interface materials to transfer heat from heat-generating electronic devices of the electronic speaker device to a housing component of the electronic speaker device. The housing component dissipates the heat to prevent a thermal runaway condition.

A cost-effective process and structure is provided for a thermal dissipation element for semiconductor device packages incorporating antennas that can incorporate RF/EMI shielding from the antenna elements. Certain embodiments provide incorporated antenna element structures as part of the same process. These features are provided using a selectively-plated thermal dissipation structure that is formed to provide shielding around semiconductor device dies that are part of the package. In some embodiments, the thermal dissipation structure is molded to the semiconductor device, thereby permitting a thermally efficient close coupling between a device die requiring thermal dissipation and the dissipation structure itself.