Methods, systems, apparatus, and articles of manufacture to control load distribution of integrated circuit packages are disclosed. An example apparatus includes a carrier plate including a first surface to face a heatsink; a second surface opposite the first surface, and an aperture extending between the first and second surfaces, the aperture dimensioned to surround a semiconductor device, and a spring carried by the carrier plate, the spring to contact a surface of the semiconductor device proximate an outer edge of the semiconductor device.

Example embodiments provide a package substrate including a lid structure. The package substrate includes a substrate, a semiconductor element arranged on one surface of the substrate, and a lid surrounding at least a portion of the semiconductor element. The lid includes a region extending outwardly beyond the outer periphery of the substrate.

Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

It is described a interconnect array device (e.g., Ball Grid Array (BGA) device) comprising (a) a substrate having a substrate body and a main surface; (b) an array of solder connection elements formed at the main surface; and (c) a support structure formed at the main surface. The support structure is configured for maintaining, during a soldering process, a predefined spacing between the main surface of the substrate and a further main surface of a component carrier onto which the Ball Grid Array is mounted. The support structure comprises at least one support element. Further described is an electronic package with such a Ball Grid Array device and a method for manufacturing an electronic assembly comprising such an electronic package mounted on a component carrier.

A semiconductor package includes a semiconductor die, a first thermal conductive pattern and a second thermal conductive pattern. The semiconductor die is encapsulated by an encapsulant. The first thermal conductive pattern is disposed aside the semiconductor die in the encapsulant. The second thermal conductive pattern is disposed over the semiconductor die, wherein the first thermal conductive pattern is thermally coupled to the semiconductor die through the second thermal conductive pattern and electrically insulated from the semiconductor die.

A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

In one general aspect, an apparatus can include a first module including a first semiconductor die, and a first heatsink coupled to the first module where the first heatsink includes a substrate and a first plurality of protrusions. The apparatus can also include a second module including a second semiconductor die, and a second heatsink coupled to the second module and including a second plurality of protrusions. The apparatus can also include a cover defining a channel where the first plurality of protrusions of the first heatsink and the second plurality of protrusions of the second heatsink are disposed within the channel.

An apparatus is provided which comprises: a die comprising an integrated circuit, a first material layer comprising a first metal, the first material layer on a surface of the die, and extending at least between opposite lateral sides of the die, a second material layer comprising a second metal over the first material layer, and a third material layer comprising silver particles and having a porosity greater than that of the second material layer, the third material layer between the first material layer and the second material layer. Other embodiments are also disclosed and claimed.

Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.