A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

Integrated circuits are supported by a semiconductor substrate wafer. Each integrated circuit includes an electrically active area. A thermally conductive protective structure is formed around the active areas of the various integrated circuits along scribe paths. The protective structure is located between the electrically active areas of the integrated circuits and a laser ablation area of the scribe paths. Separation of the integrated circuits is performed by scribing the semiconductor substrate wafer along the scribe paths. The process for scribing includes performing a laser ablation in the laser ablation area and then performing one of an etching or a physical scribing.

A semiconductor device includes a first substrate. The semiconductor device includes a plurality of metallization layers formed over the first substrate. The semiconductor device includes a plurality of via structures formed over the plurality of metallization layers. The semiconductor device includes a second substrate attached to the first substrate through the plurality of via structures. The semiconductor device includes a first conductive line disposed in a first one of the plurality of metallization layers. The first conductive line, extending along a first lateral direction, is connected to at least a first one of the plurality of via structures that is in electrical contact with a first through via structure of the second substrate, and to at least a second one of the plurality of via structures that is laterally offset from the first through via structure.

An electronic package is provided, in which an electronic element is disposed on an upper side of a circuit structure, a package layer covers the electronic element, and an action structure is embedded in the package layer, so that the action structure is exposed from a surface of the package layer, and then a bonding element is disposed on a lower side of the circuit structure and corresponding to the position of the action structure, so as to form a thermal conduction between the bonding element and the action structure. Therefore, a laser can transfer heat energy to the bonding element via the action structure, so that a solder material on the bonding element can be reflowed.

In order to reduce costs as well as to effectively dissipate heat in certain RF circuits, a semiconductor device of the circuit can include one or more active devices such as transistors, diodes, and/or varactors formed of a first semiconductor material system integrated onto (e.g., bonded to) a base substrate formed of a second semiconductor material system that includes other circuit components. The first semiconductor material system can, for example, be the III-V or III-N semiconductor system, and the second semiconductor material system can, for example be silicon.

A wiring structure includes an upper conductive structure, a lower conductive structure, an intermediate layer and at least one through via. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The through via extends through the upper conductive structure, the intermediate layer and the lower conductive structure.

An apparatus is provided which comprises: one or more pads comprising metal on a first substrate surface, the one or more pads to couple with contacts of an integrated circuit die, one or more substrate layers comprising dielectric material, one or more conductive contacts on a second substrate surface, opposite the first substrate surface, the one or more conductive contacts to couple with contacts of a printed circuit board, one or more inductors on the one or more substrate layers, the one or more inductors coupled with the one or more conductive contacts and the one or more pads, and highly thermally conductive material between the second substrate surface and a printed circuit board surface, the highly thermally conductive material contacting the one or more inductors. Other embodiments are also disclosed and claimed.

A first circuit board includes a positive output pin and a negative output pin of a power conversion circuit, each of which has a shape projecting from a second main surface. A second circuit board has a positive through via and a negative through via, each of which has a shape extending between a third main surface and a fourth main surface. The second main surface of the first circuit board and the third main surface of the second circuit board are physically in close contact with each other. The positive output pin is inserted through the positive through via to reach the fourth main surface. The negative output pin is inserted through the negative through via in such a manner as to reach the fourth main surface. The load receives a current supplied from the power conversion circuit through the positive output pin and the negative output pin.

A circuit board module includes a first circuit board having a first main surface on which an electronic component that generates heat when the electronic component operates is mounted and a second main surface, a second circuit board having a third main surface on which the first circuit board is mounted and a fourth main surface, and a first thermally-conductive sheet between the first circuit board and the second circuit board. The first circuit board is mounted such that the second main surface faces the third main surface. The first circuit board includes thermally-conductive vias that extend between the first and second main surfaces, the vias being densely distributed in a region near a mounting terminal of the electronic component, filled with a thermally-conductive member, and physically in contact with the first thermally-conductive sheet that covers the third main surface of the second circuit board.