An electrocaloric heat dissipation device is formed by inserting metal layer-pyroelectric layer-metal layer (MPM) structures between the metallization layers in a metal interconnect. Electric fields are alternately applied and relaxed to induce temperatures of the pyroelectric layers to cycle and drive heat transfer. The heat dissipation device may be placed adjacent a hot spot in a power management integrated circuit (PMIC) and is particularly useful when the PMIC is in a 3D package. In some embodiments, the MPM structures are inserted around circuit wiring. Interconnects for the heat dissipation device may replace dummy metal wiring.

A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die.

An electronic package includes a thermal interface for dissipating heat from an electronic component array including a plurality of electronic components secured to a substrate. The thermal interface includes a thin heat spreading layer for transferring heat input from the electronic components along directions transverse to heat flux. The heat spreading layer is part of a laminate structure that is efficiently utilized by spreading thermal energy across an input plane.

Provided is a semiconductor device having excellent heat dissipation capacity and electromagnetic wave suppression effect. A semiconductor device 1 includes a semiconductor device 30; a tubular conductive shield can 20 provided to surround a side surface 30a of the semiconductor device 30; a conductive cooling member 40; and a conductive thermally conductive sheet 10 formed between the semiconductor device 30 and the cooling member 40. The conductive shield can 20 and the cooling member 40 are electrically connected through the conductive thermally conductive sheet 10 therebetween.

A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Integrated circuit dies, systems, and techniques, are described herein related to efficient heat dissipation in integrated circuit implementations, such as three-dimensional packages, using integrated thermoresponsive materials. An integrated circuit die includes a thermoresponsive material in a via that extends through at least a portion of a device layer and one or more metal interconnect layers of the integrated circuit die. Such integrated circuit dies including thermoresponsive materials may be stacked vertically with their thermoresponsive material filled vias aligned.

An integrated circuit device may include an integrated circuit die coupled to a substrate, and a porous material on the die or a thermal interface material and extending beyond the edges of the die and over the substrate. An integrated circuit system may include a substrate with a power supply and an integrated circuit die, such that a porous material on the die extends over the substrate beyond a footprint of the die. A porous material may be formed on and beyond an edge of a received integrated circuit die coupled to a substrate or a thermal interface material on the die.

An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a metal foam surrounding the at least one integrated circuit device and contacting the thermal interface material. The integrated circuit assembly may further include a stiffener attached to the electronic substrate and surrounding the at least one integrated circuit device, wherein the metal foam is disposed between the stiffener, the at least one integrated circuit device, the electronic substrate, and the heat dissipation device.

An integrated circuit package that includes a leadframe and a mold compound encapsulating at least a portion of the leadframe. The mold compound includes a cavity open at a bottom surface of the mold compound that exposes a bottom surface of the leadframe. A thermally conductive and electrically insulating isolation layer is locked within the bottom cavity of the mold compound and contacts the bottom surface of the leadframe.

An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.