A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.

An immersion-type liquid cooling heat dissipation sink is provided. The immersion-type liquid cooling heat dissipation sink includes a heat dissipation substrate layer and a surface film layer. The surface film layer is formed on the heat dissipation substrate layer. The heat dissipation substrate layer is a porous substrate that is immersed in an immersion-type coolant. A contact angle between the surface film layer and the immersion-type coolant is less than a contact angle between the heat dissipation substrate layer and the immersion-type coolant. A thickness of the surface film layer is less than an effective thickness of 5 μm.

A power electronics module includes a glass layer with one or more vias extending through the glass layer and having an electrically and thermally conductive material disposed within the one or more vias, a power electronic device directly bonded to a first surface of the glass layer, and, a cooling structure thermally coupled to a second surface of the glass layer.

A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

A semiconductor chip includes semiconductor dice contained in a packaging apparatus including a cover and a plate, thereby forming a vapor chamber. The semiconductor dice and intermediate layers are alternately stacked. A capillary mechanism is provided on a horizontal internal face of the cover. Nets are provided on vertical internal faces of the cover, around the capillary mechanism. Each of the intermediate layers includes protuberances in contact with the nets. A channel is defined between any adjacent two of the protuberances. The channels travel past the intermediate layers. Coolant filled in the vapor chamber is turned into vapor after absorbing heat. The vapor ascends to the cover via the channels. The coolant is returned into liquid after transferring heat to the cover. The liquid descends to the plate. Thus, the coolant is circulated in the vapor chamber. Each of the intermediate layers includes a capillary structure to facilitate the circulation of the coolant.

A basic structural body for constructing heat dissipation device and a heat dissipation device are disclosed. The heat dissipation device includes a first basic structural body having a wick structure formed on one side surface thereof; and the first basic structural body and the wick structure are structural bodies formed layer by layer. Two pieces of first basic structural bodies can be correspondingly closed together to construct a heat dissipation device internally defining an airtight chamber. In this manner, the heat dissipation device can be designed in a more flexible manner.

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

Carrier with an electrically insulating base material, electrically conductive through-connections and a thermal connection element. The through-connections and the thermal connection element are each completely surrounded by the base material in the lateral direction, the thermal connection element and the through-connections completely penetrating the base material perpendicularly to the main extension plane of the carrier, and the thermal connection element being formed with a material which has a thermal conductivity of at least 200 W/(m K).

Disclosed is a semiconductor package including a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and laterally spaced apart from the first semiconductor chip, a dummy chip on the first semiconductor chip, and a dielectric layer between the first semiconductor chip and the dummy chip. A top surface of the first semiconductor chip may be lower than a top surface of the second semiconductor chip. The dielectric layer may include an inorganic dielectric material.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.