A semiconductor device and method for forming same. According to an embodiment. The method provides a base substrate, forms a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm.sup.−1K.sup.−1and 1200 Wm.sup.−1K.sup.−1. This method further forms a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further removes the base substrate.

A heat sink includes a channel including a gyroid structure portion having a non-uniform thickness.

Provided is a boron nitride sintered body including: a plurality of coarse particles each having a length of 20 μm or more; and fine particles smaller than the plurality of coarse particles, in which, when viewed in a cross-section, the plurality of coarse particles intersect with each other. Provided is a method for manufacturing a boron nitride sintered body, the method including: a raw material preparation step of firing a mixture containing boron carbonitride and a boron compound in a nitrogen atmosphere to obtain lump boron nitride having an average particle diameter of 10 to 200 μm; and a sintering step of molding and heating a blend containing the lump boron nitride and a sintering aid to obtain a boron nitride sintered body including coarse particles each having a length of 20 μm or more in a cross-section and fine particles smaller than the coarse particles.

A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer, an etch stop layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The etch stop layer includes silicon nitride and is disposed between the semiconductor substrate and the electrical insulating and thermal conductive layer. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

A method of forming a semiconductor structure is disclosed. The method includes forming a semiconductor wafer having a device layer situated over a handle substrate, the device layer having at least one semiconductor device, forming a front side glass on a front side of the semiconductor wafer, and partially removing the handle substrate from a back side of the semiconductor wafer. The method also includes removing a portion of the semiconductor wafer from an outer perimeter thereof, either by sawing an edge trim trench through the handle substrate, the device layer and into the front side glass to form a ring, and removing the ring on the outer perimeter of the semiconductor wafer, or by edge grinding the outer perimeter of the semiconductor wafer. The method further includes completely removing the handle substrate.

A semiconductor structure includes a semiconductor wafer having at least one semiconductor device integrated in a first device layer, a thermally conductive but electrically isolating layer on a back side of the semiconductor wafer, a front side glass on a front side of the semiconductor wafer, where the thermally conductive but electrically isolating layer is configured to dissipate heat from the at least one semiconductor device integrated in the semiconductor wafer. The thermally conductive but electrically isolating layer is selected from the group consisting of aluminum nitride, beryllium oxide, and aluminum oxide. The at least one semiconductor device is selected from the group consisting of a complementary-metal-oxide-semiconductor (CMOS) switch and a bipolar complementary-metal-oxide-semiconductor (BiCMOS) switch. The semiconductor structure also includes at least one pad opening extending from the back side of the semiconductor wafer to a contact pad.

An electronic device for use in power related applications includes a multi-layered substrate comprised of a first metal layer, a second metal layer, and an intermediate layer disposed between the first metal layer, and the second metal layer. The first metal layer is partitioned into sections, where each of the sections has a first surface and electrical circuits patterned onto the first surface. A lead frame is attached to outer portions of the first metal layer and a die is attached to the first surface of each of the sections of the first metal layer.

The present invention relates to a two-end driving, high-frequency sub-substrate structure, comprising a sub-substrate body, wherein: the sub-substrate body has an upper side provided with a first signal pad area and a second signal pad area, the first signal pad area and the second signal pad area are symmetric with respect to each other, each of the first signal pad area and the second signal pad area extends from one of two lateral portions of the sub-substrate body in an extending direction toward a center of the sub-substrate body and terminates in an end, the end of the first signal pad area is adjacent to but spaced from the end of the second signal pad area, the first signal pad area is configured for supporting a semiconductor chip provided thereon, the second signal pad area is provided with a jumper wire connected to an electrode of the semiconductor chip, there are two grounding pad areas provided respectively on two lateral sides of the first signal pad area and the second signal pad area and constituting a portion of a coplanar waveguide, the sub-substrate body has an inner layer or bottom side that is provided with a grounding layer or combined with a grounding layer.