A circuit board includes: a base body formed of ceramics or sapphire, the base body being provided with a through hole which penetrates therethrough from one principal face to another principal face of the base body; a through conductor containing silver as a major constituent, the through conductor being located inside the through hole of the base body; metallic wiring layers located on the respective principal faces of the base body and on the through conductor; and regions in which a compound containing at least one substance selected from Sn, Cu, and Ni is present between the through conductor and the metallic wiring layers.

A wafer placement table includes a ceramic substrate having a wafer placement surface on an upper surface thereof and containing an electrode therein, a cooling substrate made of a metal-ceramic composite and having a cooling medium passage therein, and a metal joining layer configured to join a lower surface of the ceramic substrate to an upper surface of the cooling substrate. A thickness of a lower part of the cooling substrate below the cooling medium passage is greater than or equal to 13 mm, or greater than or equal to 43% of an overall thickness of the cooling substrate.

The present disclosure relates to a substrate with an integrated heat spreader. The disclosed substrate includes a substrate core, at least one connecting structure, and a heat spreader. The substrate core has a top surface and a bottom surface opposite the top surface of the substrate. The at least one connecting structure extends through the substrate core from the top surface of the substrate core to the bottom surface of the substrate core. And the heat spreader extends through the substrate core from the top surface of the substrate core to a bottom level that is below the bottom surface of the substrate core.

A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

Aligned high quality boron nitride nanotubes (BNNTs) can be incorporated into groups and bundles and placed in electronic and electrical components (ECs) to enhance the heat removal and diminish the heat production. High quality BNNTs are excellent conductors of heat at the nano scale. High quality BNNTs are electrically insulating and can reduce dielectric heating. The BNNTs composite well with a broad range of ceramics, metals, polymers, epoxies and thermal greases thereby providing great flexibility in the design of ECs with improved thermal management. Controlling the alignment of the BNNTs both with respect to each other and the surfaces and layers of the ECs provides the preferred embodiments for ECs.

3D semiconductor packages and methods of forming 3D semiconductor package are described herein. The 3D semiconductor packages are formed by mounting a die stack on an interposer, dispensing a thermal interface material (TIM) layer over the die stack and placing a heat spreading element over and attached to the die stack by the TIM layer. The TIM layer provides a reliable adhesion layer and an efficient thermally conductive path between the die stack and interposer to the heat spreading element. As such, delamination of the TIM layer from the heat spreading element is prevented, efficient heat transfer from the die stack to the heat spreading element is provided, and a thermal resistance along thermal paths through the TIM layer between the interposer and heat spreading element are reduced. Thus, the TIM layer reduces overall operating temperatures and increases overall reliability of the 3D semiconductor packages.

A two-part curable composition which cures to form a thermally conductive cured product, including: (a) a first part including: (1) at least one metal catalytic component for catalyzing the cure reaction; (2) a non-reactive diluent component; (3) a wetting agent component; (4) a filler component; (5) a rheology modifier component; and (6) a pigment component; and (b) a second part including: (1) at least one silane terminated polyurethane polymer; (2) a moisture scavenger; (3) a non-reactive diluent component; (4) a filler component; and (5) a wetting agent component, wherein at least one of the filler components of the first-part and the second-part comprises a thermally conductive filler.

An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

A plug-in type power module includes a power unit and a heat-transfer unit vertically disposed on the power unit and extending outwardly away from two sides of the power unit. A first ceramic layer is disposed between the power unit and the heat-transfer unit. Therefore, heat generated by the power unit can be transferred from the first ceramic layer to the heat-transfer unit to increase the speed of heat dissipation. A subsystem having the plug-in type power module is also provided.

Embodiments herein relate to a package using aluminum oxide as an adhesion and high-thermal conductivity layer with a buildup layer having a first side and a second side opposite the first side, a first trace applied to the first side of the buildup layer, an aluminum oxide layer coupled with the first trace and an exposed area of the first side of the buildup layer, a lamination buildup layer coupled with the aluminum oxide layer on a side of the aluminum oxide layer opposite the buildup layer, wherein the lamination buildup layer includes one or more vias to the trace, and a seed layer coupled with the lamination buildup layer. Other embodiments may be described and/or claimed.