Examples of a silicon cold plate with an integrated PCB are described. An apparatus may include a silicon plate, one or more electrical and thermal connections, and a heat-generating device. The silicon plate may include a first side and a second side opposite the first side, a plurality of edges between the first side and the second side, one or more internal coolant flow channels therein, one or more coolant inlet ports disposed on one or more of the edges and configured to allow a coolant to flow into the one or more internal coolant flow channels, and one or more coolant outlet ports disposed on one or more of the edges and configured to allow the coolant to flow out of the one or more internal coolant flow channels. The one or more electrical and thermal connections may be disposed on the first side of the silicon plate. The heat-generating device may be disposed on the one or more electrical and thermal connections.

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming an isolation layer on a substrate. The isolation layer includes an opening, and a bottom of the opening exposes the substrate. The method also includes forming a fin in the opening. The fin includes a heat-dissipation region and a channel region on the heat-dissipation region. Moreover, the fin includes forming an isolation structure by removing a thickness portion of the isolation layer. A surface of the isolation structure is coplanar with a surface of the heat-dissipation region of the fin. Further, the method includes forming a channel part from the channel region by performing a thinning process to reduce a width of the channel region of the fin using the isolation structure as a mask. The heat-dissipation region of the fin forms a heat-dissipation part.

A silicon interconnect fabric includes: (1) a substrate having a front side and a back side; (2) a front side patterned metal layer on the front side of the substrate; (3) a back side patterned metal layer on the back side of the substrate; (4) multiple conductive vias extending through the substrate and connecting the front side patterned metal layer and the back side patterned metal layer; and (5) multiple conductive posts connected to the back side patterned metal layer.

A semiconductor device comprises: a substrate; a multi-layer semiconductor layer located on the substrate, the multi-layer semiconductor layer being divided into an active area and a passive area outside the active area; a gate electrode, a source electrode and a drain electrode all located on the multi-layer semiconductor layer and within the active area; and a heat dissipation layer covering at least one portion of the active area and containing a heat dissipation material. In embodiments of the present invention, a heat dissipation layer covering at least one portion of the active area is provided in the semiconductor device. The arrangement of the heat dissipation layer adds a heat dissipation approach for the semiconductor device in the planar direction, thus the heat dissipation effect of the semiconductor device is improved.

Various embodiments may relate to a liquid cooling module. The liquid cooling module may include a main body. The main body may include a cooling core including a microfluidic structure configured to carry a cooling liquid. The main body may also include a plurality of slots. The liquid cooling module may further include a sealing pad configured to transmit heat from an electronic device to the cooling core. The liquid cooling module may additionally include a plurality of fins extending from the main body, each of the plurality of fins including an internal circulating liquid duct such that the liquid cooling module includes a plurality of internal circulating liquid ducts in fluidic communication with the microfluidic structure.

A signal transmission insulating device includes: a first coil; a second coil opposing the first coil to form a transformer together with the first coil; a first insulating film provided between the opposing first coil and second coil and made of a first dielectric material; a second insulating film surrounding the first coil and made of a second dielectric material having a lower resistivity or a higher permittivity than the first dielectric material; and a third insulating film surrounding the second coil and made of a third dielectric material having a lower resistivity or a higher permittivity than the first dielectric material.

Embodiments of a silicon-based heat dissipation device and a chip module assembly are described. An apparatus may include a silicon-based heat dissipation device, an extended device coupled to the silicon-based heat-dissipation device and heat-generating devices mounted on the silicon-based heat dissipation device. The silicon-based heat dissipation device may include a base portion having a first primary side and a second primary side opposite the first primary side. The silicon-based heat dissipation device may also include a protrusion portion on the first primary side of the base portion and protruding therefrom. The protrusion portion may include multiple fins. The base portion may include a slit opening with a first heat-generating device of the heat-generating devices on a first side of the slit opening and a second heat-generating device of the heat-generating devices on a second side of the slit opening opposite the first side of the slit opening.

A material structure for silicon-based gallium nitride microwave and millimeter-wave devices and a manufacturing method thereof are provided. The material structure includes: a silicon substrate; a dielectric layer of high thermal conductivity, disposed on an upper surface of the silicon substrate, and an uneven first patterned interface being formed between the dielectric layer and the silicon substrate; a buffer layer, disposed on an upper surface of the dielectric layer, and an uneven second patterned interface being formed between the buffer layer and the dielectric layer; a channel layer, disposed on an upper surface of the buffer layer; and a composite barrier layer, disposed on an upper surface of the channel layer. In the material structure, the uneven patterned interfaces increase contact areas of the interfaces, a thermal boundary resistance and a thermal resistance of device are reduced, and a heat dissipation performance of device is improved.

The disclosure is directed to an integrated circuit (IC) die stacked with a backer die, including capacitors and thermal vias. The backer die includes a substrate material to contain and electrically insulate one or more capacitors at a back of the IC die. The backer die further includes a thermal material that is more thermally conductive than the substrate material for thermal spreading and increased heat dissipation. In particular, the backer die electrically couples capacitors to the IC die in a stacked configuration while also spreading and dissipating heat from the IC die. Such a configuration reduces an overall footprint of the electronic device, resulting in decreased integrated circuits (IC) packages and module sizes. In other words, instead of placing the capacitors next to the IC die, the capacitors are stacked on top of the IC die, thereby reducing an overall surface area of the package.

In an embodiment, a device includes: an interposer; a first integrated circuit device attached to the interposer; a second integrated circuit device attached to the interposer adjacent the first integrated circuit device; a heat dissipation die on the second integrated circuit device; and an encapsulant around the heat dissipation die, the second integrated circuit device, and the first integrated circuit device, a top surface of the encapsulant being coplanar with a top surface of the heat dissipation die and a top surface of the first integrated circuit device.