Provided is a semiconductor device that prevents resin from leaking out from a resin insulating member at a periphery of the resin insulating member and thereby achieves an increase in reliability. The semiconductor device includes a module unit, a resin insulating member bonded to the module unit, a cooling unit coupled to the module unit with the resin insulating member interposed therebetween, and a flow blocking member disposed between the module unit and the cooling unit to surround the resin insulating member, the flow blocking member being more easily compressively deformable than the resin insulating member.

A semiconductor package includes: a carrier having a first side and an opposing second side; a semiconductor die arranged on the first side of the carrier; a heat conductor part arranged on the second side of the carrier; an encapsulation body encapsulating the semiconductor die, wherein the heat conductor part is exposed from the encapsulation body, and wherein the heat conductor part has a different material composition than the encapsulation body; and a scratch protection layer covering the heat conductor part, wherein the scratch protection layer has a hardness which is at least five times higher than a hardness of the heat conductor part.

A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

A packaged power semiconductor device includes a power semiconductor wafer, a heat conduction layer, and a heat sink that are sequentially stacked, and a sealing part configured to wrap and seal the power semiconductor wafer and at least part of the heat conduction layer. The packaged power semiconductor device further includes a pin, where the pin includes a connection segment wrapped inside the sealing part, and an extension segment located outside the sealing part. The connection segment is electrically connected to the power semiconductor wafer, and a shortest distance between the extension segment and a first outer surface is greater than a creepage distance corresponding to a highest working voltage of the power semiconductor wafer. This can avoid a creepage phenomenon of the pin by limiting a distance between the first outer surface and the extension segment that is of the pin and that is exposed outside the sealing part.

A method of manufacturing a semiconductor device is provided. The method includes forming a package leadframe assembly. The package leadframe includes a plurality of leads. An adhesive is placed on a portion of the plurality of leads. A die pad is placed onto the adhesive. A portion of the die pad overlaps the portion of the plurality of leads. A semiconductor die is attached to the die pad. A molding compound encapsulates the semiconductor die and a portion of the package leadframe assembly.

A semiconductor device with high heat dissipation efficiency includes a base structure, a semiconductor chip, a heat dissipating structure, and a package body. The semiconductor chip is disposed on the base structure and has a first surface distant from the base structure. The heat dissipating structure includes a buffer layer and a first heat spreader. The buffer layer is disposed on the first surface of the semiconductor chip and a coverage rate thereof on the first surface is at least 10%. The first heat spreader is disposed on the buffer layer and bonded to the first surface of the semiconductor chip through the buffer layer. The package body encloses the semiconductor chip and the heat dissipating structure, and the package body and the buffer layer have the same heat curing temperature.

In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

A method of manufacturing a power module comprising two substrates is provided, wherein the method comprises disposing a compensation layer of a first thickness above a first substrate; disposing a second substrate above the compensation layer; and reducing the thickness of the compensation layer from the first thickness to a second thickness after the second substrate is disposed on the compensation layer.

A semiconductor device includes a semiconductor element, a lead frame, a conductive member, a resin composition and a sealing resin. The semiconductor element has an element front surface and an element back surface facing away in a first direction. The semiconductor element is mounted on the lead frame. The conductive member is bonded to the lead frame, electrically connecting the semiconductor element and the lead frame. The resin composition covers a bonded region where the conductive member and lead frame are bonded while exposing part of the element front surface. The sealing resin covers part of the leadframe, the semiconductor element, and the resin composition. The resin composition has a greater bonding strength with the lead frame than a bonding strength between the sealing resin and lead frame and a greater bonding strength with the conductive member than a bonding strength between the sealing resin and conductive member.

The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes a first chip and a second chip attached to a substrate. A thermal conductivity layer is attached to the first chip. A molding compound laterally surrounds the first chip, the second chip, and the thermal conductivity layer. The second chip extends from the substrate to an imaginary horizontally extending line that extends along a horizontally extending surface of the thermal conductivity layer facing away from the substrate. The imaginary horizontally extending line is parallel to the horizontally extending surface.