According to an aspect, a semiconductor package includes a substrate having a first surface and a second surface opposite to the first surface, a semiconductor die coupled to the second surface of the substrate, and a molding encapsulating the semiconductor die and a majority of the substrate, where at least a portion of the first surface is exposed through the molding such that the substrate is configured to function as a heat sink.

An IC package structure and an IC package unit are disclosed. The IC package includes an array of metal wall grids formed into a panel, each one of the metal wall grids having a continuous and closed metal wall to surround an IC package unit with at least one IC chip/IC die disposed therein. Each IC chip/IC die has a top surface with a plurality of metal pads formed thereon. A panel-shaped metal layer is formed on entire back side of the panel of the array of metal wall grids and bonded to the metal wall of each metal wall grid. A panel-shaped rewiring substrate having a plurality of metal pillars is connected to each IC chip/IC die with each one of the plurality of metal pillars soldered with a corresponding one of the plurality of metal pads.

A power semiconductor apparatus includes a mold portion, a panel that is conductive and in a flat plate shape, and a plurality of fins. The mold portion includes a power semiconductor element and a base plate that are molded. An opening is formed in the panel into which the base plate is inserted. The plurality of fins is fixed in grooves of the base plate. The panel has a plurality of protrusions on side surfaces forming the opening. Each protrusion has a fifth surface a cross section of which has a shape that tapers down toward an end of the protrusion, the cross section being parallel to a plane extending in the Z direction and a direction in which the protrusion protrudes. The base plate has cover portions covering the fifth surfaces, and is plastically deformed to allow the panel to be fitted in the base plate to fill gaps.

A semiconductor module may include a plurality of semiconductor elements; and a first power terminal, a second power terminal and a third power terminal electrically connected to the plurality of semiconductor elements. The plurality of semiconductor elements may include at least one upper arm switching element electrically connected between the first power terminal and the second power terminal; and at least one lower arm switching element electrically connected between the second power terminal and the third power terminal. A number of the at least one upper arm switching element may be different from a number of the at least one lower arm switching element.

A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved.

A semiconductor device includes a semiconductor element, a sealing material, and an extension wire. The semiconductor element has, on a front surface, a first electrode pad and at least one second electrode pad, and generates a current in a direction connecting the front surface and a back surface. The sealing material is made of an insulating resin material and covers a part of the front surface and a side surface of the semiconductor element. The extension wire is disposed above the semiconductor element and inside the sealing material or on the sealing material. The extension wire is electrically connected to the second electrode pad, and extends from a position inside of a contour of the semiconductor element to a position outside of the contour of the semiconductor element.

A high-resolution substrate having an area of at least 100 square centimeters and selected traces having a line/space dimension of 2 micrometers or less is employed to integrate multiple independently operable clusters of flip chip mounted components, thereby creating a circuit assembly. Each independently operable cluster of components preferably includes a power distribution chip, a test/monitor chip, and at least one redundant chip for each type of logic device and for each type of memory device. The components in at least one of the independently operable clusters of components may include the components provided in a commercially available chiplet assembly. An electronic system may comprise multiple substrates comprising independently operable clusters of components, plus a motherboard, a system controller, and a system input/output connector.

A semiconductor device includes an insulating substrate, a first and a second obverse-surface metal layers disposed on an obverse surface of the insulating substrate, a first and a second reverse-surface metal layers disposed on a reverse surface of the insulating substrate, a first conductive layer and a first semiconductor element disposed on the first obverse-surface metal layer, and a second conductive layer and a second semiconductor element disposed on the second obverse-surface metal layer. Each of the first conductive layer and the second conductive layer has an anisotropic coefficient of linear expansion and is arranged such that the direction in which the coefficient of linear expansion is relatively large is along a predetermined direction perpendicular to the thickness direction of the insulating substrate. The first and second reverse-surface metal layers are smaller than the first and second obverse-surface metal layers in dimension in the predetermined direction.

Provided is a semiconductor device including; at least a semiconductor layer; and a gate electrode that is arranged directly or via another layer on the semiconductor layer, the semiconductor device being configured in such a manner as to cause a current to flow in the semiconductor layer at least in a first direction that is along with an interface between the semiconductor layer and the gate electrode, the semiconductor layer having a corundum structure, a direction of a c-axis in the semiconductor layer being the first direction.