A heat dissipation structure, includes: a lead frame, including a high temperature pad and a low temperature pad, the high temperature pad and the low temperature pad being two portions in the lead frame which are separated from each other, wherein a high heat generation component is disposed on the high temperature pad; and a high thermal conduction element, including two sides which are respectively directly connected with the high temperature pad and the low temperature pad, to dissipate the heat energy from the high heat generation component to the low temperature pad.

A manufacturing method of an integrated circuit (IC) packaging structure includes the following steps. One or a plurality of dies is disposed on a packaging substrate. An encapsulation material is formed on the packaging substrate. The encapsulation material is configured to encapsulate the one or the plurality of the dies on the packaging substrate. At least one trench is formed in the encapsulation material. A heat dissipation structure is formed on the encapsulation material, and at least a part of the heat dissipation structure is formed in the at least one trench. The step of forming the heat dissipation structure includes the following steps. A first slurry is formed in the at least one trench, and a first curing process is performed to the first slurry for forming a first portion of the heat dissipation structure.

A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.

A power semiconductor apparatus includes a mold portion, a panel that is conductive and in a flat plate shape, and a plurality of fins. The mold portion includes a power semiconductor element and a base plate that are molded. An opening is formed in the panel into which the base plate is inserted. The plurality of fins is fixed in grooves of the base plate. The panel has a plurality of protrusions on side surfaces forming the opening. Each protrusion has a fifth surface a cross section of which has a shape that tapers down toward an end of the protrusion, the cross section being parallel to a plane extending in the Z direction and a direction in which the protrusion protrudes. The base plate has cover portions covering the fifth surfaces, and is plastically deformed to allow the panel to be fitted in the base plate to fill gaps.

A semiconductor package includes a die pad having a die attach surface, a first laterally separated and vertically offset from the die pad, a semiconductor die mounted on the die attach surface and comprising a first terminal on an upper surface of the semiconductor die, an interconnect clip that is electrically connected to the first terminal and to the first lead, and a heat spreader mounted on top of the interconnect clip. The interconnect clip includes a first planar section that interfaces with the upper surface of the semiconductor die and extends past an outer edge side of the die pad. The heat spreader covers an area of the first planar section that is larger than an area of the semiconductor die. The heat spreader laterally extends past a first outer edge side of the die pad that faces the first lead.

The present disclosure relates to a package architecture and a method for making the same. The disclosed package architecture includes a package carrier, a first device die and a second device die mounted on the package carrier, and a heat spreader. The first device die includes a first device body with a thickness between 5 μm and 130 μm, a die carrier, and an attachment section between the first device body and the die carrier, while the second device die includes a second device body. The first device body and the second device body are formed of different materials. A top surface of the die carrier of the first device die and a top surface of the second device body of the second device die are substantially coplanar. The heat spreader resides over the top surface of the die carrier and the top surface of the second device body.

A semiconductor element is mounted on a die pad, and electrode pads arranged along the outer circumference of an upper surface of the semiconductor element are electrically connected to leads by wires, respectively. The semiconductor element has an element region having a high sensitivity with respect to stress, and an element region having a relatively low sensitivity with respect to stress. A low-stress resin film is provided on the element region having a high sensitivity with respect to stress. The semiconductor element, the low-stress resin film, the die pad, and the leads are covered with an encapsulating resin.

Provided is an electric circuit body including: a power semiconductor element; a first conductor plate configured to be connected to one surface of the power semiconductor element; a first sheet-shaped member having a first resin insulation layer and configured to at least cover a surface of the first conductor plate; a sealing material configured to seal each of the power semiconductor element, the first conductor plate, and an end of the first sheet-shaped member; and a first cooling member configured to be adhesively attached to the first sheet-shaped member. In the electric circuit body, the first sheet-shaped member includes : an embedded portion where the end of the first sheet-shaped member is covered with the sealing material; a heat dissipation surface as a region to overlap the surface of the first conductor plate; and a margin as a region between the embedded portion and the heat dissipation surface, the margin is located more inward than the heat dissipation surface, and the embedded portion is located more inward than the margin.

An electronic device includes: a substrate with obverse and reverse surfaces spaced apart in a thickness direction; an electronic element having an obverse surface formed with a first obverse surface electrode; a wiring portion on the substrate obverse surface and configured to transmit a control signal for the electronic element; a conduction member with obverse and reverse surfaces spaced apart in the thickness direction, where the reverse surface is joined to the wiring portion; a conductive first lead on the substrate obverse surface; and a first connecting member joined to the obverse surface of the conduction member and the first obverse surface electrode. The first lead includes a first pad portion spaced apart from the wiring portion and to which the electronic element is joined. The wiring portion and the first obverse surface electrode are electrically connected to each other via the conduction member and the first connecting member.