Patent classifications
H01L23/4334
LOW STRESS ASYMMETRIC DUAL SIDE MODULE
Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.
SEMICONDUCTOR PACKAGES INCLUDING RECESSES TO CONTAIN SOLDER
One example of a semiconductor package includes a first substrate, a second substrate, a semiconductor die, and a spacer. The semiconductor die is attached to the first substrate. The spacer is attached to the semiconductor die and attached to the second substrate via solder. A surface of the second substrate facing the spacer includes a plurality of recesses extending from proximate at least one edge of the spacer to contain a portion of the solder.
Semiconductor package comprising a heat dissipation structure and an outer peripheral frame used as a resin flow barrier
A semiconductor package includes: an insulating substrate; a first semiconductor chip; a second semiconductor chip with a thickness smaller than a thickness of the first semiconductor chip; a heat radiation member in which a main surface located on an opposite side of an active surface of the first semiconductor chip and an active surface of the second semiconductor chip, respectively, are bonded to a lower surface; and a sealing resin having contact with at least part of a side wall of the heat radiation member without being raised over an upper surface of the heat radiation member to seal the first and second semiconductor chips on the insulating substrate, wherein in the heat radiation member, a thickness of a first bonding part to which the first semiconductor chip is bonded is smaller than a thickness of a second bonding part to which the second semiconductor chip is bonded.
Electronic device
An electronic device includes a metal member and a connected member. A metal connecting layer is provided between a lower-side surface of the metal member and an upper-side surface of the connected member, to connect the metal member and the connected member to each other. The metal connecting layer includes at least one of metal films, each of which is made of gold or gold alloy. A thickness of the metal connecting layer in an opposing area between the metal member and the connected member is smaller than a flatness of each of the lower-side surface and the upper-side surface. A rust-preventing film is formed on a side wall of the metal member in such a way that the rust-preventing film extends from an outer periphery of the metal connecting layer to a position away from the outer periphery by a predetermined distance.
Compact low inductance chip-on-chip power card
Methods, systems, and apparatuses for a power card for use in a vehicle. The power card includes an N lead frame, a P lead frame, and an O lead frame each having a body portion and a terminal portion. The O lead frame is located between the N lead frame and the P lead frame. The power card includes a first power device located between the N lead frame and the O lead frame, with a first side coupled to the body portion of the N lead frame and a second side coupled to the body portion of the O lead frame. The power card includes a second power device located between the O lead frame and the P lead frame, with a first side coupled to the body portion of the O lead frame and a second side coupled to the body portion of the P lead frame.
Chip scale package structure of heat-dissipating type
A chip scale package structure of heat-dissipating type is provided and includes a board, a die fixed on and electrically coupled to the board, a thermally conductive adhesive sheet adhered to the die, and a package body formed on the board. The die has a heat-output surface arranged away from the board. The thermally conductive adhesive sheet is connected to at least 50% of an area of the heat-output surface. The package body covers and is connected to the die and entire of the surrounding lateral surface of the thermally conductive adhesive sheet. The die is embedded in the board, the thermally conductive adhesive sheet, and the package body. The heat-dissipating surface of the thermally conductive adhesive sheet is exposed from the package body, and a thermal conductivity of the thermally conductive adhesive sheet is at least 150% of a thermal conductivity of the package body.
SEMICONDUCTOR DEVICE AND CRYSTAL GROWTH METHOD
Provided is a semiconductor device, including at least: a semiconductor layer; and a gate electrode that is arranged directly or via another layer on the semiconductor layer, the semiconductor device being configured in such a manner as to cause a current to flow in the semiconductor layer at least in a first direction that is along with an interface between the semiconductor layer and the gate electrode, the semiconductor layer having a corundum structure, a direction of an m-axis in the semiconductor layer being the first direction.
Method for Producing Power Semiconductor Module and Power Semiconductor Module
A method for producing a power semiconductor system includes packaging a power device in plastic to form a power semiconductor component, forming a first heat dissipation face on a surface of the power semiconductor component; heating a first material between a first heat sink and the first heat dissipation face; and cooling the first material on the first heat dissipation face to connect the power semiconductor component and the first heat sink.
SUBMODULE SEMICONDUCTOR PACKAGE
Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.
SEMICONDUCTOR DEVICE
A semiconductor device includes: an insulated circuit substrate including a conductive plate on a top surface side; a semiconductor chip mounted on the conductive plate; a printed circuit board provided over and electrically connected to the semiconductor chip; a first external connection terminal electrically connected to the conductive plate and extending upward from the conductive plate; a first conductive block provided to surround an outer circumference of the first external connection terminal in an insulated state; and a sealing member provided to seal the semiconductor chip, the printed circuit board, and the first conductive block.