In one example, a semiconductor device comprises a substrate and an electronic device on a top side of the substrate, a lead frame on the top side of the substrate over the electronic device, wherein the lead frame comprises a connection bar and a lead, a component mounted to the connection bar and the lead on a top side of the lead frame, and an encapsulant on the top side of the substrate, wherein the encapsulant contacts a side of the electronic device and a side of the component. Other examples and related methods are also disclosed herein.

In one general aspect, a semiconductor device package can include a die attach paddle having a first surface and a second surface that is opposite the first surface. The package can also include a semiconductor die coupled with the first surface of the die attach paddle. The package can further include a direct-bonded-metal (DBM) substrate. The DBM substrate can include a ceramic layer having a first surface and a second surface that is opposite the first surface; a first metal layer disposed on the first surface of the ceramic layer and coupled with the second surface of the die attach paddle; and a second metal layer disposed on the second surface of the ceramic layer. The second metal layer can be exposed external to the semiconductor device package. The second metal layer can be electrically isolated from the first metal layer by the ceramic layer.

A semiconductor device includes a first insulation member, a first drive conductive layer, a first semiconductor element, a second insulation member, a second drive conductive layer, a second semiconductor element, a connection member, and an encapsulation resin. The encapsulation resin encapsulates the first semiconductor element, the second semiconductor element, and the connection member. The connection member has a higher thermal conductivity than the encapsulation resin. The connection member forms a heat conduction path between the first insulation member and/or the first drive conductive layer and the second insulation member and/or the second drive conductive layer. The connection member has a higher thermal conductivity than the encapsulation resin.

A composite structure includes a first metal layer, a second metal layer, and a ceramic layer disposed therebetween. The ceramic layer has a first surface and a second surface opposite to each other and is adapted to absorb electromagnetic waves. The absorbance reaction range of the electromagnetic waves by the ceramic layer ranges from 100 MHz to 400 GHz. The first metal layer has an opening exposing the second surface. An inner sidewall of the first metal layer surrounds the opening. The orthographic projection of the second metal layer on the ceramic layer at least partially overlaps the orthographic projection of the opening on the ceramic layer. The thickness ratio of the first metal layer to the second metal layer is 1:1 to 1:2. The area ratio of the first metal layer to the second metal layer is 1:1.2 to 1:4. A package architecture including the composite structure is also provided.

A package structure includes a metal member and a resin member. The metal member has an obverse surface facing one side in a first direction. The resin member is disposed in contact with at least a portion of the obverse surface. The obverse surface has a roughened area. The roughened area includes a plurality of first trenches recessed from the obverse surface, each of the first trenches having a surface with a greater roughness than the obverse surface. The plurality of first trenches extend in a second direction perpendicular to the first direction and are next to each other in a third direction perpendicular to the first direction and the second direction. The plurality of first trenches are filled up with the resin member.

A flip-chip semiconductor package with improved heat dissipation capability and low package profile is provided. The package comprises a heat sink having a plurality of heat dissipation fins and a plurality of heat dissipation leads. The heat dissipation leads are connected to a plurality of thermally conductive vias of a substrate so as to provide thermal conductivity path from the heatsink to the substrate as well as support the heatsink to relieve compressive stress applied to a semiconductor die by the heatsink. The package further comprises an encapsulation layer configured to cover the heat dissipation leads of the heat sink and expose the heat dissipation fins of the heat sink.

A power electronic module is provided that includes an electrical connection on opposing surfaces of an electronic component that allows a high current path from a top board to a bottom board through the body of the electronic component thus improving the power electronic module's electrical resistance and reducing the current load on the connector structure which is located between the first substrate and the second substrate. The power electronic module further includes a semiconductor component positioned on an external surface of the top board which allows for thermal contact of the semiconductor component with an external heat sink thus providing an efficient system thermal management via a reduced heat dissipation path. Additional heat dissipation can be obtained by disposing a metallic spacer on the semiconductor component of the power electronic module of the present disclosure.

A transistor device according to some embodiments includes a channel layer, a barrier layer on the channel layer, and source and drain contacts on the barrier layer, and a gate contact on the barrier layer between the source and drain contacts. The channel layer includes a sub-layer having an increased doping concentration level relative to a remaining portion of the channel layer. The presence of the sub-layer may reduce drain lag without substantially increasing gate lag.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; and a die embedded in the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts and the second conductive contacts are electrically coupled to conductive pathways in the package substrate.

A semiconductor package includes an interconnect structure having a first surface and a second surface opposing the first surface, and including a redistribution pattern and a vertical connection conductor, a first semiconductor chip disposed for a first inactive surface to oppose the first surface, a second semiconductor chip disposed on the first surface of the interconnect structure and disposed for the second inactive surface to oppose the first surface; a first encapsulant encapsulating the first and second semiconductor chips, a backside wiring layer disposed on the first encapsulant, a wiring structure connecting the redistribution pattern to the backside wiring layer, a heat dissipation member disposed on the second surface and connected to the vertical connection conductor.