Described herein are integrated circuit structures having a package substrate with microstrip transmission lines as the top metallization layer, and a ground plane external to the package substrate that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit structure may include a package substrate having an internal ground plane and a microstrip signal layer as the top metallization layer, and an external ground plane on the surface of the package substrate that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit structure may further include changes to microstrip transmission line geometry to match impedance values of areas covered by the external ground plane with impedance values of areas not covered by the external ground plane.

A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.

Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.

The semiconductor device includes: a heat spreader; a first solder layer; a second solder layer; a semiconductor element including a first surface bonded to the heat spreader through the first solder layer, a second surface facing the first surface, a first electrode disposed on the first surface, and a second electrode disposed on the second surface; a block bonded to the second electrode through the second solder layer; a sheet including a first portion, and a second portion having insulating properties and being in contact with the heat spreader; a first lead frame welded to the heat spreader; a second lead frame welded to the block; and a sealant having insulating properties and sealing the first and second lead frames, the heat spreader, the first and second solder layers, the semiconductor element, and the block.

The present disclosure relates to a system in package having a chiplet with a first substrate and a first die deposed over the first substrate, a second die, a second substrate that the chiplet and the second die are deposed over, and a heatsink spreader deposed over the chiplet and the second die. Herein, the first substrate includes layered-cake shaped heatsink stanchions that are coupled to the first die, and the second substrate includes layered-cake shaped heatsink stanchions that are coupled to the chiplet and the second die. As such, heat generated by the first die can be dissipated by the heatsink stanchions within the first and second substrates, and heat generated by the second die can be dissipated by the heatsink stanchions within the second substrate. Furthermore, the heat generated by the first die and the second die can be dissipated by the heatsink spreader above them.

A package includes a conductor base plate having a element fixed to an upper surface thereof, a side wall provided on the conductor base plate to surround the element, the side wall having a conductor portion electrically connected to the conductor base plate, a dielectric cap disposed on the side wall, a front-side metal film provided on an outer surface of the dielectric cap, a first back-side metal film provided on an inner surface of the dielectric cap such that a center of the first back-side metal film approximately coincides with a center of a surface of the dielectric cap which faces the conductor base plate, and a plurality of vias passing through the dielectric cap to achieve electrical connection between the front-side metal film and the first back-side metal film and between the front-side metal film and the conductor portion oldie side wall.

Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.

The present invention relates to a power module and a manufacturing method therefor, the power module using a conductive spacer to electrically connect an electrode of a semiconductor chip and an electrode pattern of a ceramic substrate without a wire, thereby converting rated voltage and current while removing electrical risk elements, which can be generated during wire bonding, and increasing reliability and efficiency when used with high power.

A semiconductor device is provided with a first insulated substrate including an insulator layer and a metal layer disposed on each of two faces of the insulator layer, a first semiconductor element disposed on the metal layer on one face of the first insulated substrate, a second insulated substrate including an insulator layer and a metal layer disposed on each of two faces of the insulator layer, a second semiconductor element disposed on one of the metal layers of the second insulated substrate, and an encapsulant encapsulating the first semiconductor element and the second semiconductor element. The metal layer on the other face of the first insulated substrate and the metal layer on the other face of the second insulated substrate are exposed on a first flat surface of the encapsulant.

A packaged power transistor device includes a Direct-Bonded Copper (DBC) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.