A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

Semiconductor device A1 of the present disclosure includes: semiconductor element 10 (semiconductor elements 10A and 10B) having element obverse face and element reverse face facing toward opposite sides in z direction; support substrate 20 supporting semiconductor element 10; conductive block 60 (first block 61 and second block 62) bonded to element obverse face via first conductive bonding material (block bonding materials 610 and 620); and metal member (lead member 40 and input terminal 32) electrically connected to semiconductor element 10 via conductive block 60. Conductive block 60 has a thermal expansion coefficient smaller than that of metal member. Conductive block 60 and metal member are bonded to each other by a weld portion (weld portions M4 and M2) at which a portion of conductive block 60 and a portion of metal member are welded to each other. Thus, the thermal cycle resistance can be improved.

A sensor package includes a packaging formed by a package bottom, first and second sidewalls extending upwardly from first and second opposite sides of the package bottom, and third and fourth sidewalls extending upwardly from third and fourth opposite sides of the package bottom, the sidewalls and package bottom defining a cavity. An integrated circuit is attached to the package bottom. A plate extends between two of the sidewalls within the cavity and is spaced apart from the package bottom. Sensors are attached to a top surface of the plate on opposite sides of an opening. Wire bondings electrically connect pads on a top face of the sensor to corresponding pads on a top face of the integrated circuit, for example by passing through the opening in the plate or passing past a side end of the plate. A lid extends across and between the sidewalls to close the cavity.

A semiconductor device includes semiconductor chips fixed to a board, an insulating plate having a through-hole formed therein, a first lower conductor including a lower main body formed on the lower surface of the insulating plate and soldered to any of the semiconductor chips, and a lower protrusion portion that connects with the lower main body, and extends to the outside of the insulating plate, a second lower conductor formed on a lower surface of the insulating plate and soldered to any of the semiconductor chips, an upper conductor including an upper main body formed on the upper surface of the insulating plate, and an upper protrusion portion that connects with the upper main body and extends to the outside of the insulating plate, and a connection portion provided in the through-hole and connects the upper main body and the second lower conductor.

A lead frame includes an outer frame. The outer frame includes: one surface; another surface that is opposite to the one surface; a side surface between the one surface and the other surface; a recess that is formed to extend from the one surface to the side surface; and a notch step portion that is formed to extend from the other surface to the side surface.

A heat sink for cooling at least one power semiconductor module, and that includes a basin for containing a cooling liquid. The basin has a contact rim for receiving the base plate and that includes a surface that is sloped inwards to the basin.

A conductive connecting member formed on a bonded face of an electrode terminal of a semiconductor or an electrode terminal of a circuit board, the conductive connecting member comprising a porous body formed in such manner that a conductive paste containing metal fine particles (P) having mean primary particle diameter from 10 to 500 nm and an organic solvent (S), or a conductive paste containing the metal fine particles (P) and an organic dispersion medium (D) comprising the organic solvent (S) and an organic binder (R) is heating-treated so as for the metal fine particles (P) to be bonded, the porous body being formed by bonded metal fine particles (P) having mean primary particle diameter from 10 to 500 nm, a porosity thereof being from 5 to 35 volume %, and mean pore diameter being from 1 to 200 nm.

This power semiconductor device is provided with: a substrate; and a semiconductor element which is bonded onto the substrate using a sinterable metal bonding material. The semiconductor element comprises: a base; a first conductive layer that is provided on a first surface of the base, said first surface being on the substrate side; and a second conductive layer that is provided on a second surface of the base, said second surface being on the reverse side of the first surface. The thickness of the first conductive layer is from 0.5 times to 2.0 times (inclusive) the thickness of the second conductive layer.

An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.

A semiconductor device A1 includes a semiconductor element 10A having an element obverse face 101 and an element reverse face 102, the element obverse face 101 having an obverse face electrode 11 formed thereon and the element reverse face 102 having a reverse face electrode 12 formed thereon, a conductive substrate 22A including an obverse face 221A opposed to the element reverse face 102, and to which the reverse face electrode 12 is conductively bonded, a conductive substrate 22B including an obverse face 221B and spaced from the conductive substrate 22A in a width direction x, and a lead member 51 extending in the width direction x, and electrically connecting the obverse face electrode 11 and the conductive substrate 22B. The lead member 51 is located ahead of the obverse face 221B in the direction in which the obverse face 221B is oriented, and bonded to the obverse face electrode 11 via a lead bonding layer 32. The conductive substrate 22A, the semiconductor element 10A, and the lead bonding layer 32 overlap with the conductive substrate 22B, as viewed in the width direction x.