A power device cell includes: a metallic body having a first main surface, a second main surface opposite the first main surface, and a side face vertically extending between the first and second main surfaces; a vertical power semiconductor die in a recess formed in the first main surface of the metallic body; and an organic and/or glass electrical insulator covering the second main surface of the metallic body such that the power device cell is electrically insulated at least at a first side that includes the organic and/or glass electrical insulator. The organic and/or glass electrical insulator is confined to the metallic body. A backside of the vertical power semiconductor die is configured to be at a different electric potential than a frontside of the vertical power semiconductor die. The metallic body is at the same electric potential as the backside of the vertical power semiconductor die.

A method of forming a semiconductor package includes providing a first metal substrate; and mounting a stacked arrangement on the first metal substrate, the stacked arrangement comprising a semiconductor die, wherein mounting the stacked arrangement includes: providing a first layer of attachment material between the first metal substrate and the stacked arrangement; and providing a second layer of attachment material within the stacked arrangement at an interface with the semiconductor die, wherein at least one of the first and second layers of attachment material is a compressible layer that includes one or more elastomeric elements embedded within a matrix of solder material.

A semiconductor device includes an insulating substrate having an insulating plate formed of ceramic and a circuit plate fixed on a main face of the insulating plate; a semiconductor element fixed on the circuit plate; a printed circuit board disposed to face the main face of the insulating plate; a ceramic plate disposed to face the main face of the insulating plate, and arranged at a position away from the main face of the insulating plate further than the printed circuit board; a supporting member fixed to the main face of the insulating plate or to the circuit plate, to fix a position of the ceramic plate; and a resin covering the circuit plate, the semiconductor element, the printed circuit board, and the ceramic plate.

The present disclosure relates to a system in package having a chiplet with a first substrate and a first die deposed over the first substrate, a second die, a second substrate that the chiplet and the second die are deposed over, and a heatsink spreader deposed over the chiplet and the second die. Herein, the first substrate includes layered-cake shaped heatsink stanchions that are coupled to the first die, and the second substrate includes layered-cake shaped heatsink stanchions that are coupled to the chiplet and the second die. As such, heat generated by the first die can be dissipated by the heatsink stanchions within the first and second substrates, and heat generated by the second die can be dissipated by the heatsink stanchions within the second substrate. Furthermore, the heat generated by the first die and the second die can be dissipated by the heatsink spreader above them.

An object is to provide technology that enables cost reduction or downsizing of semiconductor packages. The wiring element includes a second substrate, a plurality of first relay pads arranged on a surface of the second substrate opposite to the conductor substrate and connected to each of the control pads of the plurality of semiconductor elements by wires, a plurality of second relay pads arranged on the surface of the second substrate opposite to the conductor substrate, the number thereof being equal to or lower than the number of the plurality of first relay pads, and a plurality of wiring portions arranged on the surface of the second substrate opposite to the conductor substrate and selectively connecting the plurality of first relay pads and the plurality of second relay pads.

A terminal member connected to a connection target portion includes: a bent portion bent toward the connection target portion; and a tip connection portion provided at a tip part of the bent portion, in which the tip connection portion is connected to the connection target portion via a conductive bonding material.

A circuit module includes a substrate with a patterned metal surface. The patterned metal surface includes a conductive terminal pad, a first conductive pad, and a second conductive pad that is non-adjacent to the conductive terminal pad. A first circuit portion is assembled on the first conductive pad and a second circuit portion is assembled on the second conductive pad. A conductive bridge electrically couples the conductive terminal pad and the second conductive pad. The conductive bridge includes an elevated span extending above and across the first conductive pad.

Provided is a semiconductor module comprising a power semiconductor chip, a base, an insulating substrate bonded to the base, a semiconductor chip bonded to the insulating substrate, and a case adhered to the base by means of an adhesive. The semiconductor module has a low variability but a high assembly quality and reliability enabling a decrease in stress between the case and an adhered portion of the base. The base includes a plate-like first material, and a second material coating the first material and having a linear coefficient of expansion greater than that of the first material. The case covers at least part of a side surface of the base and is adhered to the base at least on an upper surface of the base by means of the adhesive, and a linear expansion coefficient of the case is larger than the linear expansion coefficient of the first material.

The present invention discloses a packaging structure for a kiloampere-level single-switch SiC power semiconductor module, primarily including components such as SiC chips, substrates, baseplate, power and signal terminals, integrated gate/Kelvin source resistors, and housing. The packaging structure proposed in this invention improves the electrothermal performance of multi-chip SiC power modules, reduces the size of the power module, and breaks through the limitations on the number of parallel-connected SiC chips. It significantly enhances the current capacity and power density of existing SiC power semiconductor modules, making it particularly suitable for 1.7 kV6.5 kV single-switch power semiconductor modules in high-power applications such as rail transit traction and flexible DC power transmission. Furthermore, the packaging structure proposed in this invention is compatible with conventional fabrication processes such as soldering, wire bonding, and potting encapsulation. The fabrication method is mature and suitable for large-scale engineering applications.

A semiconductor device manufacturing method includes preparing a semiconductor chip and a conductive plate having a front surface that includes a disposition area on which the semiconductor chip is to be disposed, forming a supporting portion in a periphery of the disposition area of the conductive plate such that the supporting portion protrudes from a bottom of the disposition area in an upward direction orthogonal to the front surface of the conductive plate, bonding the semiconductor chip to the disposition area via bonding material applied to the disposition area, coating the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with a coating layer, and after the coating, sealing the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with sealing material.