An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.

An apparatus includes a busbar and a heat-generating electronic device mounted on a first side of the busbar, the heat-generating electronic device being electrically and thermally coupled to the first side of the busbar. The busbar includes an array of non-planar physical structures on a second side of the busbar opposite the first side of the busbar. The apparatus includes a dielectric coating on the array of non-planar physical structures, the dielectric coating defining a non-planar dielectric surface on the second side of the busbar.

A semiconductor device may be provided with a first member, a second member joined to a first region of the first member via a first solder layer and a third member joined to a second region of the first member via a second solder layer. The first region and the second region are located on one side of the first member. The first solder layer contains a plurality of support particles that is constituted of a material having a higher melting point than the first solder layer. The second solder layer does not contain any support particles.

A semiconductor device A1 includes a semiconductor element 10A having an element obverse face 101 and an element reverse face 102, the element obverse face 101 having an obverse face electrode 11 formed thereon and the element reverse face 102 having a reverse face electrode 12 formed thereon, a conductive substrate 22A including an obverse face 221A opposed to the element reverse face 102, and to which the reverse face electrode 12 is conductively bonded, a conductive substrate 22B including an obverse face 221B and spaced from the conductive substrate 22A in a width direction x, and a lead member 51 extending in the width direction x, and electrically connecting the obverse face electrode 11 and the conductive substrate 22B. The lead member 51 is located ahead of the obverse face 221B in the direction in which the obverse face 221B is oriented, and bonded to the obverse face electrode 11 via a lead bonding layer 32. The conductive substrate 22A, the semiconductor element 10A, and the lead bonding layer 32 overlap with the conductive substrate 22B, as viewed in the width direction x.

Implementations described herein are related to a semiconductor device package having an improved baseplate. In such an improved baseplate, there is a recess cut out of a region of a surface of the baseplate such that the recess has a first sidewall having a first thickness above a recess base and a second sidewall having a second thickness above the recess base. A substrate, e.g., a direct bonded copper (DBC) substrate, may be attached to the baseplate at a recess base using, e.g., a solder layer between the recess base and a surface of the substrate.

A package substrate may include a build-up layer. The build-up layer may include a dielectric material and one or more microspheres. The one or more microspheres may include a magnetic core that includes a first material that is a first oxidation-resistant material. Further, the one or more microspheres may include a shell to encapsulate the core, and the shell may include a second material that is a second oxidation-resistant material. The package substrate may further include a metal layer coupled with the build-up layer.

A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

The semiconductor device A1 includes a support member 2, a metal part 30 having obverse and reverse surfaces 301-302 spaced in z direction, with the reverse surface 302 bonded to the support member 2, a second bonding layer 42 boding the support member 2 and the metal part 30, a semiconductor element 10 facing the obverse surface 301 and bonded to the metal part 30, and a sealing member 7 covering the support member 2, metal part 30, second bonding layer 42 and semiconductor element 10. The metal part 30 includes a first body 31 of a first material and a second body 32 of a second material, with a boundary between the bodies 31-32. The second material has a linear thermal expansion coefficient smaller than that of the first material. The semiconductor device is improved in reliability by reducing thermal stress from heat generation of the semiconductor element.

A source terminal and a gate terminal are connected to a wiring pattern of the first substrate. A diode is provided under a second substrate such that an anode is connected to a wiring pattern of the second substrate. A plate-like portion of the first electrode is provided between the switching element and the diode, and a linking section of the first electrode connects the plate-like portion and the wiring pattern of the first substrate. A second electrode being substantially columnar and connecting the wiring pattern of the first substrate and the wiring pattern of the second substrate is provided in an opposite side to the linking section with the switching element interposed. A thickness of the plate-like portion of the first electrode is less than or equal to a thickness of each of the wiring pattern of the first substrate and the wiring pattern of the second substrate.

A wiring board has a metal-made base having a front surface and a back surface, an insulating frame body bonded to the front surface of the base through a bonding layer made of bonding material, a seating provided in an area that is located at an inner side with respect to the frame body on the front surface of the base, a mounting area where a component is supposed to be mounted on the front surface of the base, and a groove formed on the front surface of the base. The groove is arranged in at least an area between the mounting area and the seating on the front surface in plan view, and extends in a direction crossing an opposing direction of the mounting area and the seating.