Patent classifications
H01L23/4924
CORE-SHELL PARTICLES FOR MAGNETIC PACKAGING
A package substrate may include a build-up layer. The build-up layer may include a dielectric material and one or more microspheres. The one or more microspheres may include a magnetic core that includes a first material that is a first oxidation-resistant material. Further, the one or more microspheres may include a shell to encapsulate the core, and the shell may include a second material that is a second oxidation-resistant material. The package substrate may further include a metal layer coupled with the build-up layer.
POWER DEVICE FOR RECTIFIER
A power device for a rectifier includes a first terminal and a second terminal for connecting an external circuit, and a circuit system located between the first terminal and the second terminal. The circuit system is electrically connected to the first terminal and the second terminal. The circuit system includes a pre-molded chip and a control device. The pre-molded chip includes a transistor and a first encapsulant for encapsulating the transistor, wherein the transistor has a first electrode, a second electrode, and a third electrode. The first terminal, the second terminal and the control device are respectively electrically connected to the first electrode, the second electrode and the third electrode of the transistor.
System in package with flip chip die over multi-layer heatsink stanchion
The present disclosure relates to a system in package having a chiplet with a first substrate and a first die deposed over the first substrate, a second die, a second substrate that the chiplet and the second die are deposed over, and a heatsink spreader deposed over the chiplet and the second die. Herein, the first substrate includes layered-cake shaped heatsink stanchions that are coupled to the first die, and the second substrate includes layered-cake shaped heatsink stanchions that are coupled to the chiplet and the second die. As such, heat generated by the first die can be dissipated by the heatsink stanchions within the first and second substrates, and heat generated by the second die can be dissipated by the heatsink stanchions within the second substrate. Furthermore, the heat generated by the first die and the second die can be dissipated by the heatsink spreader above them.
SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE
An object is to provide technology that enables cost reduction or downsizing of semiconductor packages. The wiring element includes a second substrate, a plurality of first relay pads arranged on a surface of the second substrate opposite to the conductor substrate and connected to each of the control pads of the plurality of semiconductor elements by wires, a plurality of second relay pads arranged on the surface of the second substrate opposite to the conductor substrate, the number thereof being equal to or lower than the number of the plurality of first relay pads, and a plurality of wiring portions arranged on the surface of the second substrate opposite to the conductor substrate and selectively connecting the plurality of first relay pads and the plurality of second relay pads.
SEMICONDUCTOR DEVICE AND A METHOD OF ASSEMBLING A SEMICONDUCTOR DEVICE
A semiconductor assembly device is provided including a metal layer, a first metal plate, a second metal plate, a metal pillar, an encapsulant, and a die structure having a first terminal and a second terminal, the first terminal of the die structure is in electrically contact with the metal layer, the metal pillar is in electrical contact with the metal layer, and the second terminal of the die is in contact with the first metal plate and the metal pillar is in contact with the second metal plate and where between the die and the metal pillar and between the first metal plate and the second metal plate the encapsulant is provided, and at least one of the metal layer, the first metal plate or the second metal plate are made of a sintered metal powder. The disclosure also pertains to a method for manufacturing such semiconductor assembly device.
Multi-chip package with reinforced isolation
A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.
Semiconductor package and production method thereof, and semiconductor device
An object is to provide technology that enables cost reduction or downsizing of semiconductor packages. The wiring element includes a second substrate, a plurality of first relay pads arranged on a surface of the second substrate opposite to the conductor substrate and connected to each of the control pads of the plurality of semiconductor elements by wires, a plurality of second relay pads arranged on the surface of the second substrate opposite to the conductor substrate, the number thereof being equal to or lower than the number of the plurality of first relay pads, and a plurality of wiring portions arranged on the surfaceof the second substrate opposite to the conductor substrate and selectively connecting the plurality of first relay pads and the plurality of second relay pads.
DECOUPLING METHOD FOR SEMICONDUCTOR DEVICE
A sensor package includes a packaging formed by a package bottom, first and second sidewalls extending upwardly from first and second opposite sides of the package bottom, and third and fourth sidewalls extending upwardly from third and fourth opposite sides of the package bottom, the sidewalls and package bottom defining a cavity. An integrated circuit is attached to the package bottom. A plate extends between two of the sidewalls within the cavity and is spaced apart from the package bottom. Sensors are attached to a top surface of the plate on opposite sides of an opening. Wire bondings electrically connect pads on a top face of the sensor to corresponding pads on a top face of the integrated circuit, for example by passing through the opening in the plate or passing past a side end of the plate. A lid extends across and between the sidewalls to close the cavity.
HERMETIC METALLIZED VIA WITH IMPROVED RELIABILITY
An article includes a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and at least one via extending through the substrate from the first major surface to the second major surface over an axial length in an axial dimension. The article also includes a metal connector disposed within the via that hermetically seals the via. The article has a helium hermeticity of less than or equal to 1.010.sup.8 atm-cc/s after 1000 thermal shock cycles, each of the thermal shock cycle comprises cooling the article to a temperature of 40 C. and heating the article to a temperature of 125 C., and the article has a helium hermeticity of less than or equal to 1.010.sup.8 atm-cc/s after 100 hours of HAST at a temperature of 130 C. and a relative humidity of 85%.
Package with component connected with carrier via spacer particles
A package and method of making a package. In one example, the package includes an at least partially electrically conductive carrier, a passive component mounted on the carrier, and an at least partially electrically conductive connection structure electrically connecting the carrier with the component and comprising spacer particles configured for spacing the carrier with regard to the component.