A semiconductor package includes: a semiconductor device; a lead frame; a built-in package including an insulated driver having a multi-chip configuration and driving the semiconductor device; a wire connecting the built-in package to the semiconductor device; and a resin sealing the semiconductor device, the lead frame, the built-in package, and the wire, wherein the built-in package is directly joined to the lead frame.

A method of manufacturing a cascode HEMT semiconductor device including a lead frame, a die pad with an indentation attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.

A semiconductor package includes a die attach pad; a plurality of lead terminals disposed around the die attach pad; a semiconductor die mounted on the die attach pad; a molding compound encapsulating the plurality of lead terminals, the semiconductor die, and the die attach pad; and a step cut sawn into the molding compound along a perimeter of a bottom surface of the semiconductor package. The step cut penetrates through an entire thickness of each of the plurality of lead terminals, whereby each of the plurality of lead terminals has at least an exposed outer end at the step cut.

A semiconductor package comprises a lead frame, a die pad, bond pads, and leads. A die may be arranged on the die pad, the die comprising an integrated circuit. In an example, the die and at least a portion of the lead frame are encapsulated with a molding compound (MC). A first thickness of the MC over a first portion of the die is less than a second thickness over a second portion of the die to form a cavity in the MC and the MC directly contacts the first portion and the second portion of the die.

An integrated semiconductor power transistor package includes a half-bridge electrical circuit with a negative voltage outer terminal of a high-side switch connected in series with a positive voltage outer terminal of a low-side switch, a first and a second substrate, and vertical spacers. The high and the low side switches include semiconductor power transistor dies connected electrically parallel. The first substrate has a cladding layer sinter bonded to one of the semiconductor power transistor dies to define the low-side power switch. The second substrate has a first cladding layer sinter bonded to one of the semiconductor power transistor dies to define the high-side power switch, and a second cladding layer. Vertical spacers sinter bond the semiconductor power transistor die on the first substrate to the second cladding layer. Vertical spacers also sinter bond the semiconductor power transistor die on the second substrate to the cladding layer.

There is disclosed a packaged semiconductor device comprising: a leadframe having a first thickness; the leadframe comprising a die pad; a semiconductor die thereabove; and epoxy therebetween and arranged to bond the semiconductor die to the die pad; wherein in at least one region under the semiconductor die, the die pad has a second thickness less than the first thickness; wherein the die pad has at least one through-hole in the at least one region; and wherein the epoxy fills the at least one through-hole and extends thereunder and laterally beyond the through-hole. Corresponding leadframes, and an associated method of manufacture are also disclosed.

The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

The plurality of control terminals are drawn out from the first side surface of the sealing resin. The plurality of main terminals are drawn out from the second side surface of the sealing resin. Each of the main terminals includes, in the sealing resin, a bonding section wire-connected to one of the semiconductor chips, a heat transfer section adjacent to the bonding section, and a mounting section on which the other one of the semiconductor chips is mounted. A concave section is provided on the second side surface between the main terminals adjacent to each other. A side surface of the heat transfer section is opposed to the concave section. A side surface of the bonding section is not opposed to the concave section.

A chip packaging structure and a manufacturing method thereof are provided. The chip packaging structure includes a substrate, at least one first chip, an adhesive material, a redistribution circuit structure, and multiple second chips. The substrate has a first surface, a second surface opposite to the first surface, and at least one cavity. The at least one first chip is disposed in the at least one cavity. The adhesive material is disposed in the at least one cavity and located between the substrate and the at least one first chip. The redistribution circuit structure is disposed on the first surface of the substrate, and is electrically connected to the at least one first chip. The second chips are disposed on the redistribution circuit structure, and are electrically connected to the redistribution circuit structure.

In a described example, a method of forming a semiconductor apparatus includes applying a layer of an electrically insulating material on a backside of a semiconductor wafer having a plurality of integrated circuit dice. The method also includes mounting the wafer to dicing tape with a die attach film, in which the die attach film is between the backside layer and the dicing tape, and cutting the wafer into respective dice.