A network computer system verifies users for a network service using verification input provided by existing users. The network computer system may determine a set of existing users of the network service based on information obtained from an information resource of the user's computing device. The network computer system may cause a mobile device of each existing user in the set to output content that includes an identifier of the user requesting verification. The network computer system may detect a response action generated in response to the provided content from at least one existing user of the set. The network computer system may determine an account value based on each detected response action.

An improvement is achieved in the reliability of a semiconductor device. After a resin sealing portion is formed to seal a die pad, a semiconductor chip mounted over the die pad, a plurality of leads, and a plurality of wires electrically connecting a plurality of pad electrodes of the semiconductor chip with the leads, the resin sealing portion and the leads are cut with a rotary blade to manufacture the semiconductor device. In the semiconductor device, at least a portion of each of first and second leads is exposed from a lower surface of the sealing portion. End surfaces of the first and second leads as the respective cut surfaces thereof are exposed from each of side surfaces of the sealing portion as the cut surfaces of the resin sealing portion. The distance between a lower side of the end surface of the first lead and an upper surface of the sealing portion is smaller than the distance between an upper side of the end surface of the second lead adjacent thereto and the upper surface of the sealing portion.

An integrated circuit die may be fabricating to have a plurality of contacts. A metal post may be formed on each of the plurality of contacts. A plurality of bumps may be formed on a plurality of contact regions of a leadframe or on the posts, in which the plurality of bumps are formed with a material that includes metal nanoparticles. The IC die may be attached to the leadframe by aligning the metal posts to the leadframe and sintering the metal nanoparticles in the plurality of bumps to form a sintered metal bond between each metal post and corresponding contact region of the leadframe.

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

A lead frame device includes a metallic outer frame member, a lead frame package preform, and an encapsulant. The metallic outer frame member includes a pair of spaced apart longitudinal and transverse sections. The lead frame package preform includes at least one die pad surrounded by the metallic outer frame member such that a gap is formed around the die pad within the metallic, and a plurality of spaced apart leads. Each of the spaced apart leads has a first portion connected to the metallic outer frame member, a second portion proximal to and spaced apart from the die pad, a top surface, and a recess indented from the top surface. The encapsulant is filled in the recess. The disclosure also provides a lead frame device assembly.

A semiconductor device includes: a single die pad made of a metal or metal alloy and having a first surface, a second surface that is an opposite side of the first surface, and a pair of ground leads protruding from an end edge in plan view; a signal lead arranged between the ground leads; a plurality of leads arranged around the die pad in plan view; a semiconductor chip mounted on the second surface; bonding wires connecting a signal pad of the chip and the signal lead and connecting a ground pad of the chip and the ground leads; and a mold resin covering the die pad, the signal lead, the plurality of leads, the chip, and the bonding wires; wherein an interval between the signal lead and each of the ground leads is narrower than an interval between the plurality of leads.

In one example, a packaged electronic device includes a molded substrate. The molded substrate includes a conductive structure having an edge lead with an edge lead outward side and an edge lead inward side opposite to the edge lead outward side, and an inner lead having an inner lead outward side and an inner lead inward side opposite to the inner lead outward side. The molded substrate includes a substrate encapsulant covering a lower portion of the edge lead inward side, a lower portion of the inner lead inward side, and a lower portion of the inner lead outward side. An upper portion of the edge lead outward side and an upper portion of the inner lead outward side are exposed from the substrate encapsulant. An electronic component is connected to the edge lead and the inner lead. A body encapsulant covers the electronic component and portions of the conductive structure. The body encapsulant has a body encapsulant top side and body encapsulant sides, the upper portion of the edge lead outward side is exposed from one of the body encapsulant sides, and the body encapsulant covers the upper portion of the inner lead outward side and the upper portion of the inner lead inward side. A conductive cover is over the body encapsulant top side, the body encapsulant sides, and outer sides of the substrate encapsulant. The conductive cover contacts the upper portion of the edge lead outward side. Other examples and related methods are also disclosed herein.

A semiconductor package includes at least one semiconductor device situated on a leadframe island, a first at least one lead protruding from a first side of the semiconductor package and configured to provide a first electrical connection to at least one terminal of the at least one semiconductor device, a second at least one lead protruding from a second side of the semiconductor package and configured to provide a second electrical connection to the at least one terminal of the at least one semiconductor device, and a continuous conductive structure configured to provide a conductive path between the first at least one lead, the second at least one lead, and the at least one terminal of the at least one semiconductor device through the leadframe island such that the at least one semiconductor device continues to function after trimming the first at least one lead.

A semiconductor device includes a plurality of islands, each having an outer surface including an upper surface and end surfaces, semiconductor chips, above the respective islands, a bonding material, between the islands and the semiconductor chips, and plating layers, formed on the outer surfaces of the islands, and with at least one of the plurality of islands, the island is exposed as a bare surface region at a first end surface, which, among the end surfaces of the one island, faces the island adjacent thereto.

The leadframe substrate includes an isolator incorporated with metal leads by a compound layer. The metal leads are disposed about sidewalls of the isolator and provide horizontal and vertical routing for a semiconductor device to be assembled on the isolator. The compound layer covers the sidewalls of the isolator and fills in spaces between the metal leads, and provides robust mechanical bonds between the metal leads and the isolator.