Patent classifications
H01L23/49503
Method of attaching an insulation sheet to encapsulated semiconductor device
A method of manufacturing a semiconductor device, including: preparing a power semiconductor chip, a lead frame having a die pad part and a terminal part integrally connected to the die pad part, and an insulating sheet in a semi-cured state; disposing the power semiconductor chip on a front surface of the die pad part and performing wiring; encapsulating the lead frame and the power semiconductor chip with an encapsulation raw material in a semi-cured state, to thereby form a semi-cured unit, the terminal part projecting from the semi-cured unit, and a rear surface of the die pad part being exposed from a rear surface of the semi-cured unit; pressure-bonding a front surface of the insulating sheet to the rear surface of the semi-cured unit to cover the rear surface of the die pad part; and curing the semi-cured unit and the insulating sheet by heating.
WIRE BOND DAMAGE DETECTOR INCLUDING A DETECTION BOND PAD OVER A FIRST AND A SECOND CONNECTED STRUCTURES
An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and >1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.
PULSED LEVEL SHIFT AND INVERTER CIRCUITS FOR GAN DEVICES
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
BONDING STRUCTURE, SEMICONDUCTOR DEVICE, AND BONDING STRUCTURE FORMATION METHOD
A bonded structure includes a semiconductor element, an electrical conductor and a sintered metal layer. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a first direction and includes a reverse-surface electrode on the element reverse surface. The electrical conductor has a mount surface facing in a same direction as the element obverse surface and supports the semiconductor element with the mount surface facing the element reverse surface. The sintered metal layer bonds the semiconductor element to the electrical conductor and electrically connects the reverse-surface electrode and the electrical conductor. The mount surface includes a roughened area roughened by a roughening process. The sintered metal layer is formed on the roughened area.
LEAD FRAME AND PACKAGING METHOD
A lead frame includes: at least one ductile structure, including a bond area, a die paddle, or a lead finger; and at least one sacrificial structure, connected between a corresponding ductile structure and a corresponding near portion in the lead frame, wherein the near portion is a portion of the lead frame close to the ductile structure.
SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
In one example, a semiconductor device comprises a substrate having a top surface and a bottom surface, an electronic device on the bottom surface of the substrate, a leadframe on the bottom surface of the substrate, the leadframe comprising a paddle, wherein the paddle is coupled to the electronic device, and a lead electrically coupled to the electronic device. The semiconductor device further comprises a first protective material contacting the bottom surface of the substrate and a side surface of the electronic device.
ANTI-WHISKER COUNTER MEASURE USING A METHOD FOR MULTIPLE LAYER PLATING OF A LEAD FRAME
A substrate of a lead frame is made of a first material. The substrate is covered by a barrier film made of a second material, different from the first material. The barrier film is then covered by a further film made of the first material. A first portion of the lead frame is encapsulated within an encapsulating body in a way which leaves a second portion of lead frame extending out from and not being covered by the encapsulating body. A first portion of the further film which is not covered by the encapsulating body is then stripped away to expose the barrier film at the second portion of the lead frame. A second portion of the further film is left remaining encapsulated by the encapsulating body. The exposed barrier film at the second portion of the lead frame is then covered with a tin or tin-based layer.
LEAD FRAME
A lead frame includes: leads; and a dambar arranged between the leads and connecting the leads to each other, wherein each of the leads includes: a lower lead groove formed in a first surface for a wettable flank structure; and an upper lead groove formed in a second surface opposite the first surface and aligned with the lower lead groove in a thickness direction, wherein in a sawing process, a portion of the lead between the lower lead groove and the upper lead groove is at least partially removed.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE
A semiconductor device includes a semiconductor IC, a capacitor element, a support portion, a first conductor and second conductor, and a sealing body. The semiconductor IC has a first IC terminal and a second IC terminal. The capacitor element has a first terminal and a second terminal. The support portion supports the capacitor element and the semiconductor IC. The first conductor and second conductor extend so as to connect the first terminal and second terminal with, respectively, the first IC terminal and second IC terminal. The sealing body encloses the capacitor element, the semiconductor IC, the first conductor, the second conductor and the support portion. The first IC terminal and second IC terminal, the first terminal and second terminal, the first conductor and the second conductor are disposed at the inner side relative to an outer edge of the support portion.
III-NITRIDE-BASED SEMICONDUCTOR PACKAGED STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A III-nitride-based semiconductor packaged structure includes a lead frame, an adhesive layer, a III-nitride-based die, an encapsulant, and at least one bonding wire. The lead frame includes a die paddle and a lead. The die paddle has first and second recesses arranged in a top surface of the die paddle. The first recesses are located adjacent to a relatively central region of the top surface. The second recesses are located adjacent to a relatively peripheral region of the top surface. The first recess has a shape different from the second recess from a top-view perspective. The adhesive layer is disposed on the die paddle to fill into the first recesses. The III-nitride-based die is disposed on the adhesive layer. The encapsulant encapsulates the lead frame and the III-nitride-based die. The second recesses are filled with the encapsulant. The bonding wire is encapsulated by the encapsulant.