A power semiconductor module includes a substrate of planar sheet metal including a plurality of islands that are each defined by channels that extend between upper and lower surfaces of the substrate, a first semiconductor die mounted on a first one of the islands, a molded body of encapsulant that covers the metal substrate, fills the channels, and encapsulates the first semiconductor die, a hole in the molded body that extends to a recess in the upper surface of the substrate, and a press-fit connector arranged in the hole such an interior end of the press-fit connector is mechanically and electrically connected to the substrate.

A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

An electrical and/or electronic component including at least one electrical outside connecting contact. This contact is a terminal lug, which is attached at one side, for the electrical contacting with a contacting partner. The terminal lug includes a connecting side including a planar connecting surface for the electrical contacting. The exposed end of the terminal lug includes a bending leg, which is bent out of the plane by a compensating angle toward the connecting side. The bending leg includes the connecting surface. The terminal lug is designed such that, when a contacting partner, which is planar at least in this area, makes site contact with the free end of the bending leg with a force applied from the connecting side, a position orientation of the connecting surface is adaptable counter to the compensating angle until a gap-free contact is made between the connecting surface and the planar contacting partner.

A power semiconductor module having a pressure application body, a circuit carrier, which is embodied with a first conductor track, a power semiconductor element arranged thereon and an internal connecting device, and also having a housing which is embodied with a guide device arranged therein, with a connecting element. The connecting element is embodied as a bolt with first and second end sections and an intermediate section therebetween, wherein the first end section rests on the circuit carrier and is electrically conductively connected thereto; the second end section projects out of the housing through a cutout; and wherein the connecting element is arranged in the assigned guide device. The pressure application body has a first rigid partial body and a second elastic partial body, wherein the second partial body protrudes out of the first partial body in the direction of the housing.

Provided is a resin-encapsulated semiconductor device in which heat dissipation characteristic and mounting strength to a substrate are improved. Heat dissipation outer leads connected to inner leads connected to the four corners of a die pad are exposed to the outside of an encapsulating resin to improve the heat dissipation characteristic. The ends of the heat dissipation outer leads are cut in lead frame pressing, and exterior plating films are formed on the entire surfaces of the heat dissipation outer leads including the ends in exterior plating of the resin-encapsulated semiconductor device, permitting easy formation of solder fillet when the semiconductor device is mounted on a substrate.

There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Electrode pads disposed on a first surface of a semiconductor element include a first pad located close to a corner and a second pad located apart from the corner compared with the first pad. A first wire connected to the first pad has a smaller Young's modulus than a second wire connected to the second pad. A thickness of an intermetallic compound layer formed by the first wire and the first pad is larger than a thickness of an intermetallic compound layer formed by the second wire and the second pad.

An electronic device includes an electronic component provided with a first electrode pad, a die pad including an obverse surface facing in a first direction with the electronic component mounted on the obverse surface, a first lead, a second lead, and a first connection member electrically connecting the first electrode pad and the first lead to each other. The first lead and the second lead are disposed, as viewed in the first direction, on a same side of the die pad in a second direction perpendicular to the first direction. The first lead includes a first pad portion and a first extended portion. The first connection member is bonded to the first pad portion. The first extended portion extends from the first pad portion up to a position located between the die pad and the second lead as viewed in the first direction.

A semiconductor apparatus includes: a first conductor plate; a second conductor plate separated from the first conductor plate; a plurality of semiconductor devices having back surface electrodes connected to the first conductor plate; a relay substrate mounted on the second conductor plate and including a plurality of first relay pads and a second relay pad connected to the plurality of first relay pads; a plurality of metal wires respectively connecting control electrodes of the plurality of semiconductor devices to the plurality of first relay pads; a first conductor block connected to front surface electrodes of the plurality of semiconductor devices; a second conductor block connected to the second relay pad; and a sealing material sealing the first and second conductor plates, the plurality of semiconductor devices, the relay substrate, the metal wire, and the first and second conductor blocks, the sealing material includes a first principal surface and a second principal surface opposed to each other, the first conductor plate is exposed from the first principal surface, the second conductor plate is not exposed from the first principal surface, and the first and second conductor blocks are exposed from the second principal surface.