This invention provides opportunity for diamond and bi-wafer microstructures to be implemented in advanced ICs and advanced IC packages to form a new breed of ICs and SiPs that go beyond the limitations of silicon at the forefront of IC advancement due primarily to diamond's extreme heat dissipating ability. Establishing the diamond and bi-wafer microstructure capabilities and implementing them in advanced ICs and advanced IC packages gives IC and package architects and designers “an extra degree of design freedom” in achieving extreme IC performance, particularly when thermal management presents a challenge. Diamond's extreme heat spreading ability can be used to dissipate hotspots in processors and other high-power chips such as GaN HEMT, resulting in performance and reliability enhancement for IC and package applications covering HPC, AI, photonics, 5G RF/mmWave, power and IoT, and at the system level propelling the migration from traditional computing to near-memory computing and in-memory computing.

A semiconductor includes a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure and a second transistor structure, wherein the first row of terminals comprises a first gate terminal, a first sensing terminal coupled, and a first power terminal, wherein the second row of terminals, a second sensing terminal, and a second power terminal.

A semiconductor device includes first and second semiconductor elements and first and second conductive members. A first electrode on the first semiconductor element is bonded to a first stack part of the first conductive member by a first bonding layer. A second electrode on the second semiconductor element is bonded to a second stack part of the second conductive member by a second bonding layer. A first joint part of the first conductive member is bonded to a second joint part of the second conductive member by an intermediate bonding layer. A first surface of the first joint part facing the second joint part, a side surface of the first joint part continuous from the first surface, a second surface of the second joint part facing the first joint part, and a side surface of the second joint part continuous from the second surface are covered by nickel layers.

A power module is disclosed. The power module includes a first substrate, a first metal layer, at least one conductive structure and at least one power device. The first metal layer is disposed on the first substrate. The first metal layer has a first thickness d1. The first thickness d1 satisfies: 5 μm≦d1≦50 μm. The conductive structure is disposed at a position different to the first metal layer on the first substrate. The conductive structure has a second thickness d2. The second thickness d2 satisfies: d2≧100 μm. The power device is disposed on the first substrate, the first metal layer or the conductive structure. The driving electrode of the power device is electrically connected to the first metal layer. The power electrode of the power device is electrically coupled to the conductive structure.

A semiconductor device includes a chip carrier, a first semiconductor chip arranged on the chip carrier, the first semiconductor chip being located in a first electrical potential domain when the semiconductor device is operated, a second semiconductor chip arranged on the chip carrier, the second semiconductor chip being located in a second electrical potential domain different from the first electrical potential domain when the semiconductor device is operated, and an electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is designed to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other.

A transistor device includes a metal submount; a transistor die arranged on said metal submount; at least one integrated passive device (IPD) component that includes a substrate arranged on said metal submount; and one or more interconnects extending between the transistor die and the at least one integrated passive device (IPD) component. The substrate includes a silicon carbide (SiC) substrate.

A lead frame assembly includes a lead frame body, an encapsulant unit, and dicing positioning units. The lead frame body includes lead frame units, an outer frame portion extending around the lead frame units, and through holes formed on the outer frame portion. The encapsulant unit includes a lower encapsulating portion, and an upper encapsulating portion formed on the lower encapsulating portion. The dicing positioning units are respectively located at the through holes, and each includes an adhesive layer which partially fills a corresponding one of the through holes and which is formed with at least one dicing positioning hole. The dicing positioning units define at least one first dicing positioning line and at least one second dicing positioning line.

A semiconductor device, including a case that has a first power terminal including a first bonding area and a second power terminal including a second bonding area, and an insulating unit located between the first power terminal and the second power terminal, and having a shape of a flat plate, the insulating unit being bonded to the case. The insulating unit has a first insulating portion in a sheet form, and a second insulating portion which covers an upper surface, a lower surface, or both the upper and lower surfaces, of the first insulating portion. The first bonding area and the second bonding area are exposed from the insulating unit and from the case.

A semiconductor package includes a chip, a layer which is thermally coupled to the chip and which is formed from a material having a triggering temperature of greater than or equal to 200° C., starting from which an exothermic reaction takes place, and encapsulating material which at least partly covers the chip and the layer. The layer is configured in such a way and is arranged relative to the chip in such a way that, in the case of a triggered exothermic reaction of the material of the layer, at least one component of the chip is damaged on account of the temperature increase caused by the exothermic reaction.

A lead frame includes a plurality of circuit patterns which each have a die pad and an electrode terminal portion and are disposed in a band shape, a tie bar, a frame portion and a suspension lead. Cut are a connection portion between electrode terminals and the frame portion, a connection portion between the frame portion and the tie bar at both end portions in a disposition direction of circuit patterns, and a connection portion from a connection part of the frame portion with the tie bar, between the circuit patterns to a part of the frame portion extending in the disposition direction. The electrode terminal portion is bent to extend to a direction of an upper surface of a semiconductor element. The lead frame is collectively resin-sealed while exposing the tie bar and the electrode terminal portion above the tie bar.