A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces.

In one implementation, a semiconductor package includes a control transistor and a sync transistor of a power converter switching stage attached over a first patterned conductive carrier, as well as a magnetic material situated over leads of the first patterned conductive carrier. The semiconductor package also includes a second patterned conductive carrier attached over the first patterned conductive carrier, the control and sync transistors, and the magnetic material. Leads of the second patterned conductive carrier overlie the magnetic material and are coupled to the leads of the first patterned conductive carrier so as to form windings of an output inductor for the power converter switching stage, the output inductor being integrated into the semiconductor package.

An electronic component includes: a first lead frame; a second lead frame that is provided on the first lead frame; a first electronic component that is provided between the first lead frame and the second lead frame; a connection member that is provided between the first lead frame and the second lead frame; and an insulating resin that is filled between the first lead frame and the second lead frame so as to cover the first electronic component and the connection member. A first oxide film is provided on a surface of the first lead frame. A second oxide film is provided on a surface of the second lead frame. The first lead frame and the second lead frame are electrically connected to each other by the connection member.

In a described example, an apparatus includes a packaged device carrier having a board side surface and an opposing surface, the packaged device carrier having conductive leads having a first thickness spaced from one another; the conductive leads having a head portion attached to a dielectric portion, a middle portion extending from the head portion and extending away from the board side surface of the packaged device carrier at an angle to the opposing surface, and each lead having an end extending from the middle portion with a foot portion configured for mounting to a substrate.

To suppress a temperature rise of a chip accompanying a production of large output by a power converter, and to reduce a size of the power converter. A power semiconductor device includes: a first power semiconductor element to configure an upper arm of an inverter circuit; a second power semiconductor element to configure a lower arm of the inverter circuit; a first lead frame to transmit power to the first power semiconductor element; a second lead frame to transmit power to the second power semiconductor element; a first gate lead frame to transmit a control signal to the first power semiconductor element; and a sealing member to seal the first power semiconductor element, the second power semiconductor element, the first lead frame, the second lead frame, and the first gate lead frame. In the power semiconductor device, a through-hole is formed in the sealing member, and a part of the first gate lead frame and a part of the second lead frame are exposed to an inner peripheral surface of the through-hole.

In a semiconductor device, a first lead frame and a second lead frame are fixed to a metal conductor base by an organic insulating film made of a polyimide-based material. The organic insulating film satisfies relationships of t.sub.press1>t.sub.cast1 and t.sub.press2>t.sub.cast1, where t.sub.press1 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the first lead frame, t.sub.press2 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the second lead frame, and t.sub.cast1 is a thickness of a portion of the organic insulating film that is not sandwiched between the metal conductor base and the first lead frame and is not sandwiched between the metal conductor base and the second lead frame.

A method of assembling a flip chip on a leadframe package. A locking dual leadframe (LDLF) includes a top metal frame portion including protruding features and a die pad and a bottom metal frame portion having apertures positioned lateral to the die pad. The protruding features and apertures are similarly sized and alignable. A flipped integrated circuit (IC) die having a bottomside and a topside including circuitry connected to bond pads having solder balls on the bond pads is mounted with its topside onto the top metal frame portion. The top metal frame portion is aligned to the bottom metal frame portion so that the protruding features are aligned to the apertures. The bottomside of the IC die is pressed with respect to a top surface of the bottom frame portion, wherein the protruding features penetrate into the apertures.

The present disclosure relates to semiconductor components. The teachings thereof may be embodied in a lead frame for a semiconductor component including: a frame having a recess; an electrically conductive connecting element for establishing an electrical connection to the semiconductor component arranged in the recess; and an insulating element arranged in the recess and mechanically connecting the connecting element to the frame and electrically insulating it from the frame.

[Problem] An object of the present invention is to provide an electronic part mounting heat-dissipating substrate which enables a circuit for which a power semiconductor in which a large current flows is used to reduce the wiring resistances of a large power operation and improve the heat dissipation.

[Means for Solving] The present invention is an electronic part mounting heat-dissipating substrate which comprises lead frames of wiring pattern shapes formed by conductor plate and an insulating member 130 which is provided between the lead frames 110, wherein a plate surface of a part arrangement surface of said conductor plate and a top surface of said insulating member at a side of said part arrangement surface form one continuous surface, the lead frames have different thicknesses, the thick lead frame 110H is used for a large current signal and the thin lead frame 110L is used for a small current signal, a plate surface of a back surface of the part arrangement surface and a top surface of the insulating member at a side of the back surface at the part arrangement surface-side are formed in an identical plane.

An electronic heat-dissipating substrate including: lead frames of wiring pattern shapes on a conductor plate; and an insulating member between the lead frames. A plate surface of the lead frames and a top surface of the insulating member form one continuous surface. The part arrangement surface is on both surfaces of the electronic part mounting heat-dissipating substrate, a reductant circuit which includes at least similar dual-system circuit is formed on the electronic part mounting heat-dissipating substrate, a first-system circuit of the dual-system circuit is formed on a first surface of the electronic part mounting heat-dissipating substrate, a second-system circuit of the dual-system circuit is formed on a second surface of the electronic part mounting heat-dissipating substrate, and the common lead frames used in a portion of a circuit wiring are used to the first surface and the second surface of the electronic part mounting heat-dissipating substrate.