A semiconductor module includes: a semiconductor element; a first lead frame including a first portion on which the semiconductor element is mounted; a sealing member sealing the semiconductor element and the first portion; and a heat dissipation member which is integrated with the sealing member and dissipates heat generated in the semiconductor element. The heat dissipation member is insulated from the semiconductor element and the first portion by the sealing member. Therefore, the semiconductor module that is applicable to vertical semiconductor elements and ensures electrical insulation between the semiconductor element and the heat dissipation member when implementing the semiconductor module onto a circuit board, can be provided.

A power semiconductor device includes a power semiconductor element, a controlling element, a first lead frame and a second lead frame, respectively, a first metal wire electrically connecting the power semiconductor element and the first lead frame, and a sealing body covering these components. The first lead frame includes a first inner lead having a connecting surface to which one end of the first metal wire is connected. Among surfaces of the sealing body, in a side surface, a resin inlet mark is formed in a side surface portion from which the first lead frame and the second lead frame do not project, the resin inlet mark being greater in surface roughness than another area. The resin inlet mark is formed opposite to a side where the first metal wire is positioned on the connecting surface when seen in the direction along the mounting surface.

Representative implementations of devices and techniques provide isolation between a carrier and a component mounted to the carrier. A multi-layer device having lateral elements provides electrical isolation at a preset isolation voltage while maintaining a preselected thermal conductivity between the component and the carrier.

A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin, and a semiconductor chip attached to the die paddle. A first electrode, a second electrode and a third electrode of the semiconductor chip are connected to the first pin, the second pin and the die paddle respectively. A plastic package body covers the semiconductor chip, the die paddle, the first pin and the second pin. The first pin and the second pin are located near two adjacent corners of the plastic package body. The bottom surface and two side surfaces of each of the first pin and the second pin are exposed from the plastic package body. Locking mechanisms are constructed to prevent the first pin and the second pin from falling off the power semiconductor package device during a manufacturing cutting process. Portions of the first pin, portions of the second pin, and portions of the plastic package body can be cut off. Therefore, the size of the power semiconductor package device is reduced.

When a power semiconductor device is energized, heat generated from upper-side power semiconductor chips mounted on a P-potential electrode transfers to a first heat mass portion and a second heat mass portion, and heat generated from lower-side power semiconductor chips mounted on a intermediate potential electrode transfers to a resistor. A lead frame, the power semiconductor chip, an inner lead and the resistor are placed in symmetry with respect to a centerline, which can reduce the difference among the temperature increases of the power semiconductor chips when energized. In this way, transient temperature increase of the power semiconductor chip can be suppressed without adding a new member, such as a heat diffusion plate.

A second lead frame is set onto a conductive layer and a busbar. The second lead frame has holes previously formed at opposite ends thereof, and pieces of solder material or solder pieces are inserted into the holes. Then, the solder pieces are vibrated by an ultrasonically vibrating tool, whereby the solder pieces are melted without having a high temperature. The second lead frame is thus bonded to the conductive layer and the busbar. A semiconductor element and the busbar are connected by a first lead frame and the second lead frame. The connection structure thereof is such that the second lead frame to be bonded by ultrasonic bonding or other bonding methods is not directly in contact with the semiconductor element, which eliminates the risk of damage to the semiconductor element.

A semiconductor device according to the present invention includes: a semiconductor element; a first metal body having a die pad to which the semiconductor element is mounted, the semiconductor element being mounted on a die bond surface of the die pad; a second metal body which has a wire bond pad connected to a signal electrode of the semiconductor element via a wire, and is provided on the same side as the die bond surface such that the second metal body is separated from the first metal body and covered by the first metal body, the second metal body forming a transmission line together with the first metal body; and a molding resin holding the first metal body and the second metal body such that a surface of the first metal body opposite to the die bond surface is exposed.

An electronics apparatus including a first substrate having a first surface and a second surface, a first switch connected to a second switch and soldered in series on the first surface of the first substrate creating a connection to allow switching between the first switch and the second switch at high frequency, an insulation having a third surface attached to the second surface of the first substrate, and a second substrate having a pocket of low permittivity located between the first switch and the second switch on a fourth surface of the insulation, the fourth surface being opposite to the third surface where the first switch and the second switch are located.

A hermetically sealed electronics module includes a core IC installed on a substrate. A collar surrounds the core IC and is sealed to the substrate and to a lid, forming a sealed chamber. A heat spreader bonded to an internal surface of the lid extends downward into proximal thermal contact with the core IC. A thin layer of TIM can be applied between the heat spreader and core IC. The heat spreader does not overlap any tall components that extend above the core IC, and can extend over regions adjacent to the core IC. Tall components can be limited to a periphery of the chamber, and/or the heat spreader can include openings that surround central tall components. The heat spreader can be soldered or welded to the lid over an entire upper surface of the heat spreader. X-ray and/or CSAM scanning can detect heat spreader bonding flaws.

Provided is a coupled semiconductor package including at least two substrate pads; at least one semiconductor chip installed on each of the substrate pads; at least one terminal each of which is electrically connected to each substrate pad and each semiconductor chip; and a package housing covering a part of the at least one semiconductor chip and the at least one terminal, wherein lower surfaces of one or more substrate pads are formed to be electrically connected and lower surfaces of another one or more substrate pads are formed to be electrically insulated. Accordingly, partial insulation may be economically realized without applying an insulating material to a heat sink, when the package is joined to the heat sink.