A device includes an integrated circuit (IC) die, a top-side base plate to which the IC die is mounted, and a body attached to the top-side base plate such that the IC die is inside the body, the body configured for attachment to a printed circuit board (PCB) such that the top-side base plate faces away from the PCB. The device may or may not include legs that abut the PCB upon installation.

The invention discloses a package structure for better heat-dissipation or EMI performance. A first conductive element and a second conductive element are both disposed between the top lead frame and the bottom lead frame. The first terminal of the first conductive element is electrically connected to the bottom lead frame, and the second terminal of the first conductive element is electrically connected to the top lead frame. The third terminal of the second conductive element is electrically connected to the bottom lead frame, and the fourth terminal of the second conductive element is electrically connected to the top lead frame. In one embodiment, a heat dissipation device is disposed on the top lead frame. In one embodiment, the molding compound is provided such that the outer leads of the top lead frame are exposed outside the molding compound.

A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the second metal layers is provided. A first groove is formed in the first metal layer to form a chip pad and bonding pads. The bonding pads are respectively located in recesses of the chip pad. A second groove is formed in the second metal layer to form a heat-dissipation block and terminal pads. The terminal pads are respectively located in recesses of the heat-dissipation block. Conductive vias are formed to connect the corresponding terminal pads and electrically connect the bonding pads with the terminal pads. A chip is disposed on the chip pad and electrically connected to the bonding pads. An encapsulant covering the chip is formed.

A semiconductor device may include: an upper conductive plate, a middle conductive plate, and a lower conductive plate that are stacked on each other; a first semiconductor chip located between the upper conductive plate and the middle conductive plate and electrically connected to both the upper conductive plate and the middle conductive plate; and a second semiconductor chip located between the middle conductive plate and the lower conductive plate and electrically connected to both the middle conductive plate and the lower conductive plate, wherein one of an area of the upper conductive plate and an are of the lower conductive plate may be smaller than an area of the middle conductive plate, and another of the area of the upper conductive plate and the area of the lower conductive plate may be larger than the area of the middle conductive plate.

An electric drive module having a motor and an inverter that are disposed in a housing The motor includes a stator, which has a plurality of sets of windings. The inverter has a plurality of power semiconductors, which are mounted into a retaining member, an end plate, which is sealingly coupled to the retaining member, and an inlet port that extends through the end plate. Sets of the semiconductor devices are electrically coupled to corresponding sets of the windings. Power terminals on the semiconductor devices are coupled to a heat sink. Fins on the heat sinks extend into an annular region that is adjacent to axial ends of the windings. At least one of the retaining member and the end plate is sealingly coupled to the housing assembly. The inlet port, the annular region and cooling passages in the stator are coupled in fluid communication.

A method of manufacturing a semiconductor device includes forming an interlayer insulating film over a main surface of a semiconductor substrate, forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film, forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns, forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film, and forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer.

An object of the present invention is to provide a power conversion device that suppresses a bypass flow and has superior heat dissipation performance. The power conversion device according to the present invention includes a power semiconductor module 300 and a flow channel formation body 1000 on which the power semiconductor module 300 is disposed. The power semiconductor module 300 has a high thermal conductor 920 which is disposed at a position between a semiconductor chip and the flow channel formation body 1000 and a sealing material that seals a power semiconductor element and the high thermal conductor 920. The high thermal conductor 920 has a fin protruding to the flow channel formation body 1000 at the side of the flow channel formation body 1000 and a part of the sealing material surrounding the fin and a leading edge of the fin are on almost the same plane.

In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.

A power semiconductor module having a pressure application body, a circuit carrier, which is embodied with a first conductor track, a power semiconductor element arranged thereon and an internal connecting device, and also having a housing which is embodied with a guide device arranged therein, with a connecting element. The connecting element is embodied as a bolt with first and second end sections and an intermediate section therebetween, wherein the first end section rests on the circuit carrier and is electrically conductively connected thereto; the second end section projects out of the housing through a cutout; and wherein the connecting element is arranged in the assigned guide device. The pressure application body has a first rigid partial body and a second elastic partial body, wherein the second partial body protrudes out of the first partial body in the direction of the housing.