A semiconductor device includes an electric conductor, a semiconductor element, and a bonding layer. The electric conductor has a main surface and a rear surface opposite to the main surface in a thickness direction. The semiconductor element includes a main body and electrodes. The main body has a side facing the main surface of the conductor, and the electrodes each protrude toward the main surface from the side of the main body to be electrically connected to the main surface. The bonding layer is held in contact with the main surface and the electrodes. Each electrode includes a base portion in contact with the main body, and a columnar portion protruding toward the main surface from the base portion to be held in contact with the bonding layer, which is a sintered body of a metal powder.

A lead frame includes: a lead portion; a plating layer that is provided on a connected area of the lead portion, the connected area being an area connected with a semiconductor element; a recessed portion that is provided around the plating layer on the lead portion; and an oxidized layer that is provided on a surface including the recessed portion of the lead portion.

A system comprises a substrate. The substrate comprises a lead. The system also comprises a solder barrier formed on the lead. The solder barrier is to contain a solder bump within a solder area on the lead. The system further includes a solder bump in the solder area and a die having an active surface coupled to the solder bump.

Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

A system and method comprising depositing a first layer on a substrate, in which the first layer comprises at least one of, a metal oxide and carbon based derivative, wherein the first layer is a gate electrode of a tag. Depositing a second layer, annealing said second layer, and treating a surface of the second layer, wherein the surface treatment is configured to enhance conductivity. Depositing a third layer, wherein the third layer is a gate dielectric of the tag. Depositing a fourth and a fifth layer. The fifth layer comprises at least an Indium Gallium Zinc Oxide layer and as a semiconductor layer of the tag. Photonic curing the fifth layer. Depositing a sixth and a seventh layer, in which the sixth layer is a source contact layer and said seventh layer is a drain contact layer of the tag.

Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

A display device includes a display panel, a main circuit board facing a rear surface of the display panel and including a first main segment, a second main segment, and a first sub-segment disposed between the first main segment and the second main segment, and flexible printed circuit boards which electrically connects the display panel and the main circuit board. A first cut-away portion is defined between the first main segment and the second main segment, the first main segment is bent along a first bending line defining a boundary between the first main segment and the first sub-segment, and the second main segment is bent along a second bending line defining a boundary between the second main segment and the first sub-segment.

Described examples include, an integrated circuit package having a die with a surface and at least two bond pads in the first surface. The integrated circuit package also includes at least two leads having a first portion and a second portion, the die coupled to the first portion and the at least two bond pads having a conductive connection the leads, the first portion of the at least two leads having a first width greater than a second width of the second portion. The integrated circuit package also including an encapsulation covering the die and the first portion of the at least two leads, the second portion of the at least two leads extending outside of the encapsulation such that a surface of the second portion is parallel with a surface of the encapsulation and the second portion extends beyond the encapsulation less than a thickness of the encapsulation.

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

In a described example, an apparatus includes: a package substrate for mounting a semiconductor die to a die side surface, the package substrate including leads spaced from one another; and cavities extending into the leads from the die side surface, the cavities having sides and a bottom surface of the lead material, the cavities at locations corresponding to post connect locations on the semiconductor die.