An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.

In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.

An assembly comprises a circuit board structure and a plurality of connection portions. The circuit board structure has a main circuit board and a supplemental circuit board. The main circuit board is formed with an accommodating portion. The accommodating portion is recessed downward in an up-down direction from an upper surface of the main circuit board. The main circuit board has a plurality of upper main conductive portions which are formed on the upper surface of the main circuit board. The supplemental circuit board has a plurality of upper supplemental conductive portions which are formed on an upper surface of the supplemental circuit board. The supplemental circuit board is, at least in part, accommodated in the accommodating portion. Each of ones of the connection portions connects a respective one of the upper main conductive portions and a respective one of the upper supplemental conductive portions with each other.

A package including an electronic leadless module having a top side, a bottom side and side faces between the top side and the bottom side, the electronic leadless module having an electronic circuit, a plurality of electrical contact pads at the bottom side of the electronic leadless module which are electrically conductively coupled to the electronic circuit, and encapsulation material which partially encapsulates the electronic circuit, wherein the electrical contact pads are at least partially free from encapsulation material and the electronic leadless module have an anchoring region on at least one side face. The package may also include a carrier frame which carries the electronic leadless module, with the side face extending further in the direction of the carrier frame below the anchoring region than in the anchoring region, and filler material in the anchoring region for fastening the electronic leadless module to the carrier frame.

A leadless semiconductor package includes a plurality of internal gull wing leads forming a concave region and an IC die disposed in the concave region and having a plurality of conductive bumps at a first surface connected to corresponding proximal sections of the internal gull wing leads. Distal ends of the internal gull wing leads form surface mount pads at a mounting surface of the leadless semiconductor package for mounting the package to a circuit board. Packaging encapsulant extends between the mounting surface and an opposing surface of the package and encapsulates the first surface of the IC die and the proximal ends of the internal gull wing lead structures. In some implementations, the mounting surface further includes a second surface of the IC die opposite the first surface and thus a thermally conductive material may be disposed between the second surface of the IC die and the circuit board.

A package, able to encapsulate at least one component, forming a closed cavity of Faraday cage type having side walls resting on a base and that are surmounted by a cover, wherein at least one of the side walls includes exterior electrical connection elements linked electrically to the interior of the cavity, the exterior connection elements able to interconnect with an exterior circuit such that the side wall faces the exterior circuit when the exterior connection elements are interconnected with the circuit.

According to one embodiment, a semiconductor device includes a first substrate, a second substrate, a first electronic component, a heat-conducting layer, a covering portion, and a heat-transporting portion. The first substrate has a first face and the second substrate has a second face and a third face. The first electronic component has a fourth face and a fifth face. The heat-conducting layer covers the third face and the fifth face. The covering portion covers at least the heat-conducting layer. The heat-transporting portion thermally connects the heat-conducting layer and the first substrate, and is located outside the second substrate and outside the covering portion.

An electronic power device including: a first electronic power component in which all the electrodes are arranged at a first main face of the first electronic power component; and an electric contact element in which a first main face is arranged against the first main face of the first electronic power component and which includes plural separate electrically conductive portions to which the electrodes of the first electronic power component are electrically connected. The first electronic power component and the electric contact element together form a stack such that a first lateral face of each of the portions of the electric contact element, substantially perpendicular to the first main face of the electric contact element, is arranged against at least one metallization of a support forming an electric contact of the first electronic power component.

A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.

A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure, a redistribution line, and a seal ring structure. The redistribution line and the seal ring structure are in the dielectric structure, the seal ring structure continuously surrounds the redistribution line, the seal ring structure includes a first seal ring and a second seal ring over and electrically connected to the first seal ring, and the redistribution structure has a first sidewall, a first surface, and a second surface opposite to the first surface. The chip package structure includes a chip structure over the first surface. The chip package structure includes a ground bump over the second surface. The chip package structure includes a conductive shielding film covering the chip structure and the first sidewall of the redistribution structure.