A multi-piece wiring substrate includes a matrix substrate including first and second insulating layers, and interconnection substrate regions arranged in a matrix. The matrix substrate includes dividing grooves opposing each other and disposed along boundaries between the interconnection substrate regions, and through-holes penetrating the matrix substrate in a thickness direction at positions where the dividing grooves are disposed. The inner surface conductor gradually decreases in thickness from a thick portion in a middle of the inner surface conductor, to thin portions disposed on a side of a boundary between the first and second insulating layers and on a first main surface side, and includes inclination portions each of which gradually increases in thickness from a boundary between corresponding one of the dividing grooves and the inner surface conductor to an inner surface of the inner surface conductor, in vertical sectional view.

A semiconductor device includes a molded body and an interconnection layer. The molded body includes a semiconductor chip, at least one terminal body disposed around the semiconductor chip and a resin member provided between the semiconductor chip and the terminal body. The molded body has a first surface, a second surface opposite to the first surface and a side surface connected to the first and second surfaces. The interconnection layer is provided on the first surface of the molded body. The interconnection layer includes an interconnect electrically connecting the semiconductor chip and the terminal body. The terminal body has first and second contact surfaces. The first contact surface is exposed at the first or second surface of the molded body. The second contact surface is connected to the first contact surface and exposed at the side surface of the molded body.

The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

A module has electronic components mounted to a Printed Circuit Board (PCB) with multiple patterned conductive layers connecting to conductive slot metal around a conductive slot. A groove is cut through a top molding encapsulant above and into the conductive slot but does not cut through a bottom molding encapsulant. A terminal pin is inserted into the groove and pushed down into the conductive slot. When heated, embedded solder previously applied to the conductive slot metal flows between the end of the terminal pin and the conductive slot metal to form a solder bond. An end of the PCB past the conductive slot has no metal traces, preventing shorts. Epoxy can be placed into the groove around the terminal pin or a hole formed in the terminal pin to increase strength of the anchored terminal pin. The molding around the groove protects terminal pins from shorting from the side.

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.

A semiconductor device includes a leadframe that includes contact pins and a semiconductor die that has protruding connection formations. A flexible support member is disposed between the leadframe and the semiconductor die and supports the semiconductor die. The flexible support member has electrically conductive lines that extend between the leadframe and the semiconductor die. The electrically conductive lines of the flexible support member are electrically coupled with the contact pins of the leadframe and with the connection formations of the semiconductor die.

A method of manufacturing a ceramic package is provided. An electrically conductive paste is applied to an inside of the first hole and an inside of the second hole of a ceramic green sheet. A ceramic member including first and second electrically conductive members is formed by burning the ceramic green sheet. The ceramic member is divided so as to divide each of the first and second electrically conductive members. A distance between first and second connecting portions is smaller than each of a length of the first connecting portion in a first direction and a length of the second connecting portion in a second direction. The length of the first connecting portion in the first direction is larger than a length of the first connecting portion in a third direction. The length of the second connecting portion has a similar relation.

A wiring board (1) includes an insulating substrate (11) having a cutout (12) opened in a main surface and a side surface of the insulating substrate (11), and an inner electrode (13) formed on an inner surface of the cutout (12). The inner electrode (13) includes a plurality of metal layers. The inner electrode (13) includes, as an intermediate layer, at least one metal layer (17b) selected from the group consisting of a nickel layer, a chromium layer, a platinum layer, and a titanium layer, and includes a gold layer as an outermost layer (17a). The metal layer (17b) is exposed at an outer edge portion of the inner electrode (13).

A wiring substrate comprises an insulating substrate and an external electrode on the insulating substrate. The insulating substrate comprises a lateral surface comprising a cutout. The cutout extends to a lower surface of the insulating substrate. The external electrode extends from an inner surface of the cutout to the lower surface of the insulating substrate. The insulating substrate comprises a protrusion at a lower end portion of the inner surface of the cutout. The protrusion protrudes from the inner surface of the cutout toward the lateral surface of the insulating substrate.