A semiconductor device comprises a lead, a board, and an electrically conductive layer on the board. The lead comprises a longitudinal axis and is soldered to the electrically conductive layer. The semiconductor device further comprises a first solder dam edge and a second solder dam edge, each positioned on the lead not more than 10 mils apart from each other along the longitudinal axis.

A semiconductor device includes: an insulating substrate; a first conductor portion and a second conductor portion that are formed on the insulating substrate; a semiconductor element disposed on the first conductor portion; a first terminal that is connected to a first electrode of the semiconductor element; a second terminal that is connected to the first conductor portion; a connection member electrically connecting a control electrode of the semiconductor element and the second conductor portion to each other; a support member that is disposed at a predetermined distance from the second conductor portion; a pin terminal having that is supported in a state of being inserted through the support member and connected to the second conductor portion; and a sealing resin that seals the insulating substrate, the first conductor portion, the second conductor portion, the semiconductor element, the connection member, and the support member.

A terminal member connected to a connection target portion includes: a bent portion bent toward the connection target portion; and a tip connection portion provided at a tip part of the bent portion, in which the tip connection portion is connected to the connection target portion via a conductive bonding material.

A semiconductor device includes: plural conductor portions formed on an insulating substrate; a semiconductor element disposed on one of the plural conductor portions on the insulating substrate; a support member that is disposed at a predetermined distance from one of the plural conductor portions on the insulating substrate; a columnar pin terminal that is supported by the support member and is connected to the one of the plural conductor portions on the insulating substrate from which the support member is disposed at the predetermined distance; and a sealing resin that seals the insulating substrate, the plural conductor portions, the semiconductor element, and the support member. The support member has a through-hole having a polygonal shape and penetrating in a plate thickness direction of the support member, and the pin terminal is supported by the support member in a state in which the pin terminal is inserted through the through-hole.

A semiconductor device includes: an insulating substrate; a first conductor portion and a second conductor portion that are formed on the insulating substrate; a semiconductor element disposed on the first conductor portion; a first terminal having a flat plate-shape that is connected to a first electrode of the semiconductor element; a second terminal having a flat plate-shape that is connected to the first conductor portion; and a sealing resin that seals the insulating substrate, the first conductor portion, the second conductor portion, and the semiconductor element. Each of the first terminal and the second terminal includes: an inner terminal portion disposed inside the sealing resin; and an outer terminal portion disposed in a state of being exposed to an exterior of the sealing resin, and a female thread portion is provided in the outer terminal portion of each of the first terminal and the second terminal.

A semiconductor package includes an interposer including first and second surfaces opposite to each other. The semiconductor package also includes a heat dissipation layer disposed on the first surface of the interposer and a first semiconductor die mounted on the first surface of the interposer. The semiconductor package additionally includes a stack of second semiconductor dies mounted on the second surface of the interposer. The semiconductor package further includes a thermally conductive connection part for transferring heat from the stack of the second semiconductor dies to the heat dissipation layer.

A method of fabrication a package and a stencil structure are provided. The stencil structure includes a first carrier having a groove and stencil units placed in the groove of the first carrier. At least one of the stencil units is slidably disposed along sidewalls of another stencil unit. Each of the stencil units has openings.

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes an interposer substrate over the wiring substrate. The interposer substrate includes a redistribution structure, a dielectric layer, a conductive via, and a plurality of first dummy vias, the dielectric layer is over the redistribution structure, the conductive via and the first dummy vias pass through the dielectric layer, the first dummy vias surround the conductive via, and the first dummy vias are electrically insulated from the wiring substrate. The chip package structure includes a chip structure over the interposer substrate. The chip structure is electrically connected to the conductive via, and the chip structure is electrically insulated from the first dummy vias.

Provided is a semiconductor package having a package housing in an engraved surface form and a method of manufacturing the same, wherein the semiconductor package includes: at least one substrate on which at least one semiconductor chip is installed; at least one terminal lead electrically connected to the substrates; electrical connectors for connecting the semiconductor chips to the substrates or the terminal leads; a package housing covering the semiconductor chips, the electrical connectors, and the at least one substrate; at least one stopper which is formed of a material same as that of the package housing, is higher by a certain height than exposed surfaces of the substrates, is disposed on the exposed surfaces of the substrates, or covers at least a part of the exposed surfaces; and at least one heat sink transmitting heat from the semiconductor chips and radiating heat, wherein the at least a part of the exposed surfaces of the at least one substrate is formed on the upper surface, the lower surface, or the upper and lower surfaces of the package housing and the exposed surfaces of the at least one substrate are joined to the heat sinks by using heat transfer connectors interposed therebetween. Accordingly, the full thickness of the heat transfer connectors may be uniformly maintained.

A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.