A method for forming a semiconductor structure includes curing a shape memory polymer in a first shape. The shape memory polymer is coupled to a conductive layer. The method further includes folding the shape memory polymer from the first shape into a second shape. The method also includes bonding a semiconductor wafer to the conductive layer while the shape memory polymer is in the second shape. The semiconductor wafer has first and second dies. The semiconductor wafer is then singulated to separate the first die from the second die. The method further includes expanding the shape memory polymer to its first shape and singulating the shape memory polymer to separate the first and second dies.

A circuit board includes a board, first connection pads disposed on the board and arranged in a first direction, second connection pads disposed on the board and arranged in the first direction, a driving chip disposed on the board and between the first connection pads and the second connection pads, and a first adhesive layer disposed on the board and overlapping with an entirety of the first connection pads in a plan view. The second connection pads are spaced apart from the first connection pads in a second direction perpendicular to the first direction.

A chip on film for a display device, the chip on film includes: a base substrate; a lead wire disposed on the base substrate; and a driving chip connected to the lead wire, wherein the lead wire includes: a first lead part having a first thickness; and a second lead part disposed between the first lead part and the driving chip and having a second thickness greater than the first thickness, the second lead part being connected to the driving chip. The first lead part and the second lead part include a same material.

A circuit module is provide that includes a substrate including a first surface and a second surface that are opposite to each other, an IC mounted on the first surface of the substrate, a circuit disposed on the first surface and the second surface of the substrate with a conductor pattern obtained by heat curing of conductive paste, and connected between the IC and an external circuit, and a dummy conductor pattern obtained by heat curing of the conductive paste, disposed on at least one of the first surface and the second surface of the substrate, and configured to maintain a balance of the conductive paste on the first surface and the second surface of the substrate.

Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

The present application provides a display panel, a manufacturing method of the display panel, and a display terminal. The display panel includes a base substrate. The base substrate comprises a first substrate, a semi-interpenetrating net structure layer, and a second substrate stacked on each other. The semi-interpenetrating net structure layer is formed by curing after interpenetration between a material of the first substrate in a partially cured state and a material of the second substrate in an uncured state. Accordingly, a bonding strength between the first and second substrates is increased, inert properties between them are reduced, and production yields in separating a glass substrate from the first substrate are improved.

A power semiconductor module includes a substrate with a structured metallization layer and a number of semiconductor chips. Each chip has a first power electrode bonded to the metallization layer. A leadframe is laser-welded to second power electrodes of the semiconductor chips for electrically interconnecting the semiconductor chips. A control conductor is attached to the leadframe opposite to the semiconductor chips and is electrically isolated from the leadframe. The control conductor is electrically connected to control electrodes of the semiconductor chips in the group.

A semiconductor device includes: an insulated circuit substrate including first and second conductive layers on a top surface side; a first semiconductor chip mounted on the first conductive layer; a second semiconductor chip mounted on the second conductive layer; a printed circuit board including a first lower-side wiring layer arranged to be opposed to the first semiconductor chip, and a second lower-side wiring layer arranged to be opposed to the second semiconductor chip, the printed circuit board being provided with a curved part curved toward the insulated circuit substrate; a first connection member arranged to connect the first semiconductor chip with the first lower-side wiring layer; a second connection member arranged to connect the second semiconductor chip with the second lower-side wiring layer; and a third connection member arranged to connect the first conductive layer with the second lower-side wiring layer at the curved part.

Embodiments disclosed herein include package substrates with antennas on the core. In an embodiment, a package substrate comprises a core with a first surface and a second surface. In an embodiment, a first conductive plane is formed into the core, where the first conductive plane is substantially orthogonal to the first surface, and a second conductive plane is formed into the core, where the second conductive plane is substantially orthogonal to the first surface. In an embodiment, an antenna is on the core, where the antenna is between the first conductive plane and the second conductive plane.

A display panel and a display device are provided. The display panel includes: a first substrate including a display area and a wiring area, wherein active switches and pixel units are disposed in the display area, and the pixel units couple to the active switches; a second substrate disposed opposite the first substrate; a first drive line portion disposed in the wiring area and including first circuit leads; a second drive line portion disposed in the wiring area and including second circuit leads; a first interface unit connected to the first circuit leads; and a virtual bit interface unit connected to the second circuit leads. The first drive line portion is mounted around the second drive line portion, and the first interface unit is connected to the virtual bit interface unit, so the second drive line portion is coupled to the first drive line portion to form parallel circuits.