A display device includes a display panel, first and second insulating layers, and a high refractive insulating layer. The display panel includes emission areas and a non-emission area. The first insulating layer is disposed on the display panel, and first openings are defined in the first insulating layer. Second openings, corresponding to the first openings, are defined in the second insulating layer having a refractive index greater than that of the first insulation layer. The high refractive insulating layer has a refractive index greater than that of the second insulating layer. The high refractive insulating layer is disposed on the first and second insulating layers. The first insulating layer includes a first inclined surface defining the first openings, and the second insulating layer includes a second inclined surface defining the second openings. The first inclined surface and the second inclined surface are spaced apart from each other.

A chip on film package structure including a flexible film, a patterned metal layer, a chip, a patterned solder resist layer, and a code-included pattern is provided. The flexible film comprises a chip mounting region and a peripheral region surrounding the chip mounting region. The patterned metal layer disposed on the flexible film. The chip mounted on the chip mounting region and electrically connected to the patterned metal layer. The patterned solder resist layer exposing the chip mounting region and covering a part of the patterned metal layer. The code-included pattern disposed on the peripheral region of the flexible film. The code-included pattern comprises a plurality of machine-readable data. A method for reading a code-included pattern on a package structure is also provided.

A chip on film package is provided. The chip on film package includes a film substrate with a base film, a conductive pad extending in a first direction on the base film, and a conductive line pattern extending from the conductive pad; a semiconductor chip provided on the film substrate; and a bump structure provided between the semiconductor chip and the conductive pad. A first peripheral wall and a second peripheral wall of the bump structure extend in the first direction and define a trench, a portion of the conductive pad is provided in the trench, and the conductive pad is spaced apart from at least one of the first peripheral wall and the second peripheral wall.

An integrated circuit comprises a substrate including a shape memory polymer, and a semiconductor die mounted on the substrate.

A foil package includes a first foil substrate with a first and a second main surface, a second foil substrate with a first and a second main surface, wherein its first main surface is arranged facing the second main surface of the first foil substrate. The foil package includes at least one electronic device arranged between the first foil substrate and the second foil substrate and a first electrically conductive layer structure structured into a plurality of first partial areas arranged on the second main surface of the first foil substrate. The plurality of partial areas incompletely cover the second main surface of the first foil substrate. The at least one electronic device includes a terminal side and a side opposite to the terminal side.

A chip-on-film package includes a base film having a top surface and a bottom surface, and a circuit region; a source driver chip and a gate driver chip mounted on the circuit region; a first conductive line on the top surface of the base film, a second conductive line on the bottom surface of the base film, and a conductive via that connects the first and second conductive lines to each other; a first row of bonding pads on the circuit region and connected to the source driver chip; a second row of bonding pads on the circuit region and connected to the source driver chip and the gate driver chip; and a test pad outside the circuit region and connected to the first and second conductive lines and the conductive via.

A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.

An embedded packaging structure and a manufacturing method thereof are disclosed. The method includes: providing a bearing plate with a first metal seed layer; processing on the first metal seed layer to obtain a substrate; removing the bearing plate to obtain the substrate, and processing on the substrate to obtain a first and a second cavities penetrating therethrough; assembling a first component in the first cavity, assembling a connecting flexible board in the second cavity, processing on a second side of the substrate to obtain a second insulating layer; processing on a first side of the substrate to obtain a second circuit layer, assembling a second component on the second circuit layer; bending the substrate through the connecting flexible board to form an included angle less than 180 degrees on the first side, and packaging the first side by using a packaging material to obtain a packaging layer.

A method and system for heat bonding a chip to a substrate by means of heat bonding material disposed there between. At least the substrate is preheated from an initial temperature to an elevated temperature below a damage temperature of the substrate. A light pulse applied to the chip momentarily increases the chip temperature to a pulsed peak temperature below a peak damage temperature of the chip. The momentarily increased pulsed peak temperature of the chip causes a flow of conducted heat from the chip to the bonding material, causing the bonding material to form a bond.

An electronic device including a connection element is provided. The connection element includes a first insulation layer and a second insulation layer. The first insulation layer has a first opening. A sidewall of the first insulation layer at the first opening has roughness different from roughness of a top surface of the first insulation layer. The second insulation layer is disposed on the first insulation layer, and the second insulation layer has a second opening. The sidewall of the first insulation layer at the first opening is exposed by the second opening. A method of fabricating an electronic device is also provided.