A smart card including a card body having a metal layer including a recess area which opens onto a peripheral edge of the metal layer, an RF chip, a first RF antenna connected to the RF chip and disposed in or facing the recess area, and a second RF antenna electrically insulated from the metal layer and from the first RF antenna. The second RF antenna includes a first antenna part extending facing the metal layer to collect an image current induced by first eddy currents flowing in the metal layer, and a second antenna part electrically connected to the first antenna part and extending facing the recess area to allow a magnetic coupling between the first RF antenna and the second RF antenna.

A package including an electronic leadless module having a top side, a bottom side and side faces between the top side and the bottom side, the electronic leadless module having an electronic circuit, a plurality of electrical contact pads at the bottom side of the electronic leadless module which are electrically conductively coupled to the electronic circuit, and encapsulation material which partially encapsulates the electronic circuit, wherein the electrical contact pads are at least partially free from encapsulation material and the electronic leadless module have an anchoring region on at least one side face. The package may also include a carrier frame which carries the electronic leadless module, with the side face extending further in the direction of the carrier frame below the anchoring region than in the anchoring region, and filler material in the anchoring region for fastening the electronic leadless module to the carrier frame.

A semiconductor package includes a chip, a layer which is thermally coupled to the chip and which is formed from a material having a triggering temperature of greater than or equal to 200° C., starting from which an exothermic reaction takes place, and encapsulating material which at least partly covers the chip and the layer. The layer is configured in such a way and is arranged relative to the chip in such a way that, in the case of a triggered exothermic reaction of the material of the layer, at least one component of the chip is damaged on account of the temperature increase caused by the exothermic reaction.

A submount for connecting a semiconductor device to an external circuit, the submount comprising: a planar substrate formed from an insulating material and having relatively narrow edge surfaces and first and second relatively large face surfaces; at least one recess formed along an edge surface; a layer of a conducting material formed on a surface of each of the at least one recess; a first plurality of soldering pads on the first face surface configured to make electrical contact with a semiconductor device; and electrically conducting connections each of which electrically connects a soldering pad in the first plurality of soldering pads to the layer of conducting material of a recess of the at least one recess.

An electromagnetic communication device includes a device substrate, an antenna formed on or in the device substrate, and a circuit element having an electrical circuit and one or more electrically conductive connection posts protruding from the circuit element. Each of the connection posts is electrically connected to the electrical circuit and at least one connection post is electrically connected to the antenna.

Method for producing at least one electronic chip support, from a plate that includes a first face intended to be in contact with a chip reader, a second face, covered with a first layer of electrically conductive material and intended to be linked to a radio antenna, and a core made from an electrically insulating material separating the first face from the second face. This method includes steps of drilling at least one through hole through the plate, depositing a layer of electrically conductive material on the first face and chemically etching a first electric circuit and a second electric circuit on the first face and the second face respectively. Prior to the chemical etching step, a step of depositing a third layer of electrically conductive material in the hole or holes, which covers the electrically insulating material in the corresponding hole or holes.

An information processing device that includes a coil antenna is configured to receive an external magnetic field and thereby generate power, and a first IC chip and a second IC chip each connected in parallel to the coil antenna and configured to receive power supplied from the coil antenna. Power received by the first IC chip from the coil antenna is different from power received by the second IC chip from the coil antenna.

A chip card substrate is provided, which includes a plurality of layers. The plurality of layers includes a first polymer layer including a first polymer material, a second polymer layer disposed over the first polymer layer and a second polymer material different from the first polymer material. The plurality of layers further includes a third polymer layer disposed over the second polymer layer and including the first polymer material. The second polymer layer includes a plurality of cutouts at an edge of the second polymer layer so that the first polymer material of the first polymer layer and of the third polymer layer form a coupling through the plurality of cutouts.

A semiconductor package can include a semiconductor chip on a substrate inside the semiconductor package and an electrode pad spaced apart from the semiconductor chip on the substrate inside the semiconductor package. A wire can be inside the semiconductor package, to connect the electrode pad to the semiconductor chip and a barrier member can be on the substrate fencing-in the semiconductor chip, where the electrode pad and the wire can be in an interior portion of the substrate. A sealing material can be in the interior portion of the substrate fenced-in by the barrier member, where the sealing material covering the semiconductor chip, the electrode pad, and the wire.

A semiconductor device including a memory cell is provided. The memory cell comprises a transistor, a memory element and a capacitor. One of first and second electrodes of the memory element and one of first and second electrodes of the capacitor are formed by a same metal film. The metal film functioning as the one of first and second electrodes of the memory element and the one of first and second electrodes of the capacitor is overlapped with a film functioning as the other of first and second electrodes of the capacitor.